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Fri, 12 Jan 2018 19:43:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea9vM-0006am-S6 for qemu-devel@nongnu.org; Fri, 12 Jan 2018 19:43:56 -0500 Received: from mout.kundenserver.de ([217.72.192.75]:56211) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea9vM-0006Zv-HZ for qemu-devel@nongnu.org; Fri, 12 Jan 2018 19:43:52 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue103 [212.227.15.183]) with ESMTPSA (Nemesis) id 0LdtKd-1fIbQb0l3j-00j3je; Sat, 13 Jan 2018 01:43:50 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 13 Jan 2018 01:43:37 +0100 Message-Id: <20180113004338.16867-7-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180113004338.16867-1-laurent@vivier.eu> References: <20180113004338.16867-1-laurent@vivier.eu> X-Provags-ID: V03:K0:vbBdCvJ6QpRrDd+uK04ItJVuuHhznDNz5ldtcjxQUBvzZKx1Cwx h7VPUDfOzjWOt8GDsdIhxTwNl+MvdTDWSzUylu8vjskHQX9D1+gDfnnnuc+bPyGDY1q0p2L vJJtvRJ920P5SUaeGitdZmf3WFiDpN8P9DDjDw2Koh4WoR/RrhD96irJUTsimlu+JxUV4lQ HbFynwx8PED3aRAJ+iDGA== X-UI-Out-Filterresults: notjunk:1;V01:K0:sQU4XEn+CuM=:H6C/GWxvlayD1ZsTo2+h7h BGyJDvJ6cNFqQ2go6X4Xj8hhXsNVztdU2lrOlQCx51UdyRoK5Kxk9MAkf3K6lRgFqjxYSv+Qv a7DionUKZaCIE74VBlvrkPWIi+86g07GiEDVgV/z86Z36ReVDK8HxD4zfnhX0GaUWoMUCxP8y +8h1RCMPnwczmdelJjob7S49cBwmBMAkE/i1kOdktppbC0sN4wMvNY1EbboOBUdxQM0KrgyOi EPtKWpFyq4YT/zEJf5zSQ9aNIlGLISNK8s96U+VjEapK6k5QiMuzdhU7789pIvt0RUnmKEwGV I6wWGHgtMkY9wcthBcmwt6SdxFVsdNJuJ75pvagalOMuv/BV4ULLeJUWnUDJf9JX13ki1hWEe vMKvUAhChzJ2IEoQWThV0ZjSmdTZeB6JB0faD8u1jExAMjXrVQmHXai1m85wwL6dTs9L6A+RT HgyWn9GZJh2tBRI5xuYgs1Iqd3F6Ele5I1WY7yyY/ZDRitLixsY04z8H6W+Whc5PhuNjxGZl2 YzaplLQa6zP09weoxt5hGBlNGWiMsILlQLXY3Jw0bHnSeLzFxyzWHM451i2WSK1xmgkzSLpOp mj3WVycJYfuG49O2/6mlhxE6nM001yfZvZi0RV2VY/VRKCFSD/Tbc85aaRd/ZBvRI+nSpnzQk YuCdhIemlxkT0GU2k4cFBBfpSaJh88Iy5hWEWxVgO+u2x+IB52dzBYzqYBo0aEEi4TfilTwCo 8rYtMqWrDvsIorhDahBaHpN1bV0IVBgFgPb/SQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.72.192.75 Subject: [Qemu-devel] [PATCH v2 6/7] target/m68k: add pflush/ptest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- v2: change ACCESS_PTEST value because of new ACCESS_DEBUG use -page_size to mask address instead of TARGET_PAGE_MASK target/m68k/cpu.h | 3 +++ target/m68k/helper.c | 72 +++++++++++++++++++++++++++++++++++++++++++++= ++++ target/m68k/helper.h | 2 ++ target/m68k/monitor.c | 1 + target/m68k/op_helper.c | 1 + target/m68k/translate.c | 33 +++++++++++++++++++++++ 6 files changed, 112 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4f09888de4..bb890f0561 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -131,6 +131,7 @@ typedef struct CPUM68KState { uint32_t srp; bool fault; uint32_t ttr[4]; + uint32_t mmusr; } mmu; =20 /* Control registers. */ @@ -510,6 +511,8 @@ enum { ACCESS_STORE =3D 0x02, /* 1 bit to indicate debug access */ ACCESS_DEBUG =3D 0x04, + /* PTEST instruction */ + ACCESS_PTEST =3D 0x08, /* Type of instruction that generated the access */ ACCESS_CODE =3D 0x10, /* Code fetch access */ ACCESS_DATA =3D 0x20, /* Data load/store access */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index c1bd0e9681..6950c03ada 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -221,6 +221,9 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t = reg, uint32_t val) case M68K_CR_TC: env->mmu.tcr =3D val; return; + case M68K_CR_MMUSR: + env->mmu.mmusr =3D val; + return; case M68K_CR_SRP: env->mmu.srp =3D val; return; @@ -272,6 +275,8 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uin= t32_t reg) /* MC680[34]0 */ case M68K_CR_TC: return env->mmu.tcr; + case M68K_CR_MMUSR: + return env->mmu.mmusr; case M68K_CR_SRP: return env->mmu.srp; case M68K_CR_USP: @@ -434,6 +439,10 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, for (i =3D 0; i < M68K_MAX_TTR; i++) { if (check_TTR(env->mmu.TTR(access_type, i), prot, address, access_type)) { + if (access_type & ACCESS_PTEST) { + /* Transparent Translation Register bit */ + env->mmu.mmusr =3D M68K_MMU_T_040 | M68K_MMU_R_040; + } *physical =3D address; *page_size =3D TARGET_PAGE_SIZE; return 0; @@ -462,6 +471,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -479,6 +491,9 @@ static int get_physical_address(CPUM68KState *env, hwad= dr *physical, stl_phys(cs->as, entry, next | M68K_DESC_USED); } if (next & M68K_DESC_WRITEPROT) { + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D M68K_MMU_WP_040; + } *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { return -1; @@ -526,6 +541,12 @@ static int get_physical_address(CPUM68KState *env, hwa= ddr *physical, page_offset =3D address & ~page_mask; *physical =3D (next & page_mask) + page_offset; =20 + if (access_type & ACCESS_PTEST) { + env->mmu.mmusr |=3D next & M68K_MMU_SR_MASK_040; + env->mmu.mmusr |=3D *physical & 0xfffff000; + env->mmu.mmusr |=3D M68K_MMU_R_040; + } + if (next & M68K_DESC_WRITEPROT) { *prot &=3D ~PAGE_WRITE; if (access_type & ACCESS_STORE) { @@ -1079,6 +1100,57 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_= t val, uint32_t acc) } =20 #if defined(CONFIG_SOFTMMU) +void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + hwaddr physical; + int access_type; + int prot; + int ret; + target_ulong page_size; + + access_type =3D ACCESS_PTEST; + if (env->dfc & 4) { + access_type |=3D ACCESS_SUPER; + } + if ((env->dfc & 3) =3D=3D 2) { + access_type |=3D ACCESS_CODE; + } + if (!is_read) { + access_type |=3D ACCESS_STORE; + } + + env->mmu.mmusr =3D 0; + env->mmu.ssw =3D 0; + ret =3D get_physical_address(env, &physical, &prot, addr, + access_type, &page_size); + if (ret =3D=3D 0) { + tlb_set_page(cs, addr & -page_size, + physical & -page_size, + prot, access_type & ACCESS_SUPER ? + MMU_KERNEL_IDX : MMU_USER_IDX, page_size); + } +} + +void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) +{ + M68kCPU *cpu =3D m68k_env_get_cpu(env); + + switch (opmode) { + case 0: /* Flush page entry if not global */ + case 1: /* Flush page entry */ + tlb_flush_page(CPU(cpu), addr); + break; + case 2: /* Flush all except global entries */ + tlb_flush(CPU(cpu)); + break; + case 3: /* Flush all entries */ + tlb_flush(CPU(cpu)); + break; + } +} + void HELPER(reset)(CPUM68KState *env) { /* FIXME: reset all except CPU */ diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 57f210aa14..7f400f0def 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -101,5 +101,7 @@ DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) =20 #if defined(CONFIG_SOFTMMU) +DEF_HELPER_3(ptest, void, env, i32, i32) +DEF_HELPER_3(pflush, void, env, i32, i32) DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env) #endif diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index c31feb4b02..486213cd8b 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -39,6 +39,7 @@ static const MonitorDef monitor_defs[] =3D { { "dttr1", offsetof(CPUM68KState, mmu.ttr[M68K_DTTR1]) }, { "ittr0", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR0]) }, { "ittr1", offsetof(CPUM68KState, mmu.ttr[M68K_ITTR1]) }, + { "mmusr", offsetof(CPUM68KState, mmu.mmusr) }, { NULL }, }; =20 diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 4609caa546..ffea9693fc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -466,6 +466,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, bool is_write, } =20 if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr =3D 0; env->mmu.ssw |=3D M68K_ATC_040; /* FIXME: manage MMU table access error */ env->mmu.ssw &=3D ~M68K_TM_040; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6972913984..0ebd786ba4 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4673,6 +4673,35 @@ DISAS_INSN(cinv) /* Invalidate cache line. Implement as no-op. */ } =20 +#if defined(CONFIG_SOFTMMU) +DISAS_INSN(pflush) +{ + TCGv opmode; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + opmode =3D tcg_const_i32((insn >> 3) & 3); + gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); + tcg_temp_free(opmode); +} + +DISAS_INSN(ptest) +{ + TCGv is_read; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + is_read =3D tcg_const_i32((insn >> 5) & 1); + gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); + tcg_temp_free(is_read); +} +#endif + DISAS_INSN(wddata) { gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); @@ -5864,6 +5893,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(cpushl, f428, ff38, CF_ISA_A); INSN(cpush, f420, ff20, M68040); INSN(cinv, f400, ff20, M68040); + INSN(pflush, f500, ffe0, M68040); + INSN(ptest, f548, ffd8, M68040); INSN(wddata, fb00, ff00, CF_ISA_A); INSN(wdebug, fbc0, ffc0, CF_ISA_A); #endif @@ -6071,6 +6102,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n", env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1], env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]); + cpu_fprintf(f, "MMUSR %08x, fault at %08x\n", + env->mmu.mmusr, env->mmu.ar); #endif } =20 --=20 2.14.3