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[50.78.183.178]) by smtp.gmail.com with ESMTPSA id t80sm20197600pgb.88.2018.01.12.13.06.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jan 2018 13:06:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=asCrjqWvKzTme/l8ME07J3gKo4r8k8Aqe9Mx+ApiovU=; b=T51lj+NZ7KaQZCf2b0xkEfj4ZZPgdNoYBd264Hy+EfvD7bFW3ab1ekvce8FBPhpktq JH+mj/bTxyHp+Sk/w+8jgzu+tEbfP0HcM1yi6k2hwRNQIshUIW3I4qyO6EuCYE7tv97i lq87Oxie0ypgOUx5+bhKybxzMdgJtYYsPA2dQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=asCrjqWvKzTme/l8ME07J3gKo4r8k8Aqe9Mx+ApiovU=; b=OZ4W1X2prpQ30oXlyyCachXvsWRBXHoVzBJ03RZsY503pAEc97mtcDYbGJWHNf+CAr LLlIjzVmF3O1clOXMr4/OMu/UVkvMmVUyySp2SSnC50XL7c84ZoqSBf8ZirmsZSYEneC kwlW+n309+qWxmRvwSkToPJr3zqBu+4GDEG3ek6FlKnrwo9rqHKLvL62I3h+9p3rPeLF HnckZKTfQQiuX3GjaCC/YvBLnV0K8bSGDvX4kbsx8nFmy7yG7ho5M3xkSoEkBojaZZFz sBdgYqg2+DZ/FcXaS6C66YRLtVtvVyavolLpJBj9zXw9BSNq98GmHm9XUOV5LhKylu/z 8VDg== X-Gm-Message-State: AKGB3mKnez3DWkxqv9/DSN/xajkKBCbJVVBVdN5lXs7dyB8u1GHyVbPe oJYKuEB9a4r+5b7F5sv1iPD3YoXfODQ= X-Google-Smtp-Source: ACJfBouieitnz7c6S9CS3JInmK/Uaq4OdH6ZPbAMoVkiYvC9rJ4TK7RbbFh5LAzvZkEz0Bcq2+g3Hw== X-Received: by 10.159.194.195 with SMTP id u3mr22056561plz.416.1515791178488; Fri, 12 Jan 2018 13:06:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 12 Jan 2018 13:06:10 -0800 Message-Id: <20180112210613.14124-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180112210613.14124-1-richard.henderson@linaro.org> References: <20180112210613.14124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL 1/4] tcg/arm: Fix double-word comparisons X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 112 +++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 80 insertions(+), 32 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 98a12535a5..b9890c8bd8 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -239,10 +239,11 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int = type, } } =20 -#define TCG_CT_CONST_ARM 0x100 -#define TCG_CT_CONST_INV 0x200 -#define TCG_CT_CONST_NEG 0x400 -#define TCG_CT_CONST_ZERO 0x800 +#define TCG_CT_CONST_ARM 0x0100 +#define TCG_CT_CONST_INV 0x0200 +#define TCG_CT_CONST_NEG 0x0400 +#define TCG_CT_CONST_INVNEG 0x0800 +#define TCG_CT_CONST_ZERO 0x1000 =20 /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, @@ -258,6 +259,9 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, case 'N': /* The gcc constraint letter is L, already used here. */ ct->ct |=3D TCG_CT_CONST_NEG; break; + case 'M': + ct->ct |=3D TCG_CT_CONST_INVNEG; + break; case 'Z': ct->ct |=3D TCG_CT_CONST_ZERO; break; @@ -351,8 +355,7 @@ static inline int check_fit_imm(uint32_t imm) static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) { - int ct; - ct =3D arg_ct->ct; + int ct =3D arg_ct->ct; if (ct & TCG_CT_CONST) { return 1; } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { @@ -361,6 +364,9 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, return 1; } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) { return 1; + } else if ((ct & TCG_CT_CONST_INVNEG) + && check_fit_imm(~val) && check_fit_imm(-val)) { + return 1; } else if ((ct & TCG_CT_CONST_ZERO) && val =3D=3D 0) { return 1; } else { @@ -1103,6 +1109,64 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg = a0) } } =20 +static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGReg al =3D args[0]; + TCGReg ah =3D args[1]; + TCGArg bl =3D args[2]; + TCGArg bh =3D args[3]; + TCGCond cond =3D args[4]; + int const_bl =3D const_args[2]; + int const_bh =3D const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + /* We perform a conditional comparision. If the high half is + equal, then overwrite the flags with the comparison of the + low half. The resulting flags cover the whole. */ + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, ah, bh, const= _bh); + tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, al, bl, const= _bl); + return cond; + + case TCG_COND_LT: + case TCG_COND_GE: + /* We perform a double-word subtraction and examine the result. + We do not actually need the result of the subtract, so the + low part "subtract" is a compare. For the high half we have + no choice but to compute into a temporary. */ + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, al, bl, const= _bl); + tcg_out_dat_rIK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CP= SR, + TCG_REG_TMP, ah, bh, const_bh); + return cond; + + case TCG_COND_LE: + case TCG_COND_GT: + /* Similar, but with swapped arguments. And of course we must + force the immediates into a register. */ + if (const_bl) { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP, bl); + bl =3D TCG_REG_TMP; + } + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, bl, al, 0); + if (const_bh) { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP, bh); + bh =3D TCG_REG_TMP; + } + tcg_out_dat_rIK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CP= SR, + TCG_REG_TMP, bh, ah, 0); + return tcg_swap_cond(cond); + + default: + g_assert_not_reached(); + } +} + #ifdef CONFIG_SOFTMMU #include "tcg-ldst.inc.c" =20 @@ -1964,22 +2028,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], arg_label(args[3])); break; - case INDEX_op_brcond2_i32: - /* The resulting conditions are: - * TCG_COND_EQ --> a0 =3D=3D a2 && a1 =3D=3D a3, - * TCG_COND_NE --> (a0 !=3D a2 && a1 =3D=3D a3) || a1 !=3D a3, - * TCG_COND_LT(U) --> (a0 < a2 && a1 =3D=3D a3) || a1 < a3, - * TCG_COND_GE(U) --> (a0 >=3D a2 && a1 =3D=3D a3) || (a1 >=3D a3 = && a1 !=3D a3), - * TCG_COND_LE(U) --> (a0 <=3D a2 && a1 =3D=3D a3) || (a1 <=3D a3 = && a1 !=3D a3), - * TCG_COND_GT(U) --> (a0 > a2 && a1 =3D=3D a3) || a1 > a3, - */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[0], args[2], const_args[2]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], - arg_label(args[5])); - break; case INDEX_op_setcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[1], args[2], const_args[2]); @@ -1988,15 +2036,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], ARITH_MOV, args[0], 0, 0); break; + + case INDEX_op_brcond2_i32: + c =3D tcg_out_cmp2(s, args, const_args); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + break; case INDEX_op_setcond2_i32: - /* See brcond2_i32 comment */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[2], args[4], const_args[4]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], + c =3D tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0,= 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; =20 @@ -2093,9 +2141,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef sub2 =3D { .args_ct_str =3D { "r", "r", "rI", "rI", "rIN", "rIK" } }; static const TCGTargetOpDef br2 - =3D { .args_ct_str =3D { "r", "r", "rIN", "rIN" } }; + =3D { .args_ct_str =3D { "r", "r", "rIM", "rIM" } }; static const TCGTargetOpDef setc2 - =3D { .args_ct_str =3D { "r", "r", "r", "rIN", "rIN" } }; + =3D { .args_ct_str =3D { "r", "r", "r", "rIM", "rIM" } }; =20 switch (op) { case INDEX_op_goto_ptr: --=20 2.14.3 From nobody Fri Mar 29 12:53:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515791297602587.9670116238894; Fri, 12 Jan 2018 13:08:17 -0800 (PST) Received: from localhost ([::1]:38896 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6Yb-0000zq-KF for importer@patchew.org; Fri, 12 Jan 2018 16:08:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6Ws-0008Mx-AR for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea6Wr-0002lx-CU for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:22 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:36127) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea6Wr-0002lR-6Z for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:21 -0500 Received: by mail-pg0-x241.google.com with SMTP id j2so5355981pgv.3 for ; Fri, 12 Jan 2018 13:06:21 -0800 (PST) Received: from cloudburst.twiddle.net (50-78-183-178-static.hfc.comcastbusiness.net. [50.78.183.178]) by smtp.gmail.com with ESMTPSA id t80sm20197600pgb.88.2018.01.12.13.06.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jan 2018 13:06:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AyEats20dBLg765p+pFXKeVHxfgYwUJeYJhOT46OMcg=; b=P1EH4iiV+/8WNSso9ra1eaIPsM+9zAhAUmKnjInsp7SbZZTVSRnE3OxjHX7QxqQP1T p/v/FuGnj0Dk3uJEfD5rUiL6ENjJhtbnHNiyJITXMDvP8C7pPv8NKeZkRS60c6F/D159 QMaFdlkm7pRcTDZXxoKFJm0f3aEDQMyHeR1Mk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AyEats20dBLg765p+pFXKeVHxfgYwUJeYJhOT46OMcg=; b=Qdf8J2l091QNVWQWik/FwDBZj5gCpN0wwMJ8IwxBl5cU9iYS8iQ0GOIns01OVH6LSZ SpVRteM0Ndat9S0I2yOsNhl3vvbVwNbFEV1Ien5TJ3B6GePL9T/9dH6G/47PkL1op3E7 K3nJ2u35wwZaTOjPEMLuYcI7NGn0obVj36357xNrhW0U400iMxuFbpSITGwkmQunDxP3 KGaD8DWczuBF6hd6gDsMXKceB6amcx8mYLhvbmS/HHW3jEwtyz8brHInQL+/L3UwolaW kTbtOQlHsCJ1ZNZkipaiqiKkSpjw+ufAhegNAbMiraGyVdgBXZdh4yAXjZhnzaP5TzZJ t0Zg== X-Gm-Message-State: AKGB3mKrfGVbyQD0WU60EhIBibMzlrxUUS8RbtT5xI3It+AifI7Lzkiv WbBvblXIPPPave4oWaaXGPgqExf1xv0= X-Google-Smtp-Source: ACJfBosizQoN9ZHJWT5gQjc+Gpi/xUcbxk9tHY/lxtlzqS7y0OzV4wuYknw9NanTlc3eKr/8OFifPQ== X-Received: by 10.84.236.70 with SMTP id h6mr26707653pln.256.1515791179941; Fri, 12 Jan 2018 13:06:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 12 Jan 2018 13:06:11 -0800 Message-Id: <20180112210613.14124-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180112210613.14124-1-richard.henderson@linaro.org> References: <20180112210613.14124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 2/4] tcg/arm: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index b9890c8bd8..4bd465732b 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1261,12 +1261,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGRe= g argreg, /* We're expecting to use an 8-bit immediate and to mask. */ QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); =20 -/* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset. - Using the offset of the second entry in the last tlb table ensures - that we can index all of the elements of the first entry. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) - > 0xffff); - /* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ =20 @@ -1279,6 +1273,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); int add_off =3D offsetof(CPUArchState, tlb_table[mem_index][0].addend); + int mask_off; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 @@ -1310,16 +1305,25 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } =20 - /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff - || (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64 - && cmp_off > 0xff)) { + /* Add portions of the offset until the memory access is in range. + * If we plan on using ldrd, reduce to an 8-bit offset; otherwise + * we can use a 12-bit offset. */ + if (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64) { + mask_off =3D 0xff; + } else { + mask_off =3D 0xfff; + } + while (add_off > mask_off) { + int shift =3D ctz32(cmp_off & ~mask_off) & ~1; + int rot =3D ((32 - shift) << 7) & 0xf00; + int addend =3D cmp_off & (0xff << shift); tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, - (24 << 7) | (cmp_off >> 8)); + rot | ((cmp_off >> shift) & 0xff)); base =3D TCG_REG_R2; - add_off -=3D cmp_off & 0xff00; - cmp_off &=3D 0xff; + add_off -=3D addend; + cmp_off -=3D addend; } + if (!use_armv7_instructions) { tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); --=20 2.14.3 From nobody Fri Mar 29 12:53:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515791510726759.9508052927133; Fri, 12 Jan 2018 13:11:50 -0800 (PST) Received: from localhost ([::1]:39099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6cA-0003x4-19 for importer@patchew.org; Fri, 12 Jan 2018 16:11:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6Wt-0008O5-Fe for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea6Ws-0002n7-KQ for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:23 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34990) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea6Ws-0002mS-Fb for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:22 -0500 Received: by mail-pg0-x244.google.com with SMTP id d6so5353089pgv.2 for ; Fri, 12 Jan 2018 13:06:22 -0800 (PST) Received: from cloudburst.twiddle.net (50-78-183-178-static.hfc.comcastbusiness.net. [50.78.183.178]) by smtp.gmail.com with ESMTPSA id t80sm20197600pgb.88.2018.01.12.13.06.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jan 2018 13:06:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=UPjYkbOAH/mxRFSgXKUOK2HXSnmj55DtWMlDR2vsIQuw6iGRFiTZxLmZ1KLqQHSbwX PLuoY2+DrMipZDNKMMoM3TvTHaDF6Zfyy7DbqE7KqJa0XcuR8mD+H/RwfDZjX8w8bG9y 1nShs3LPs/JpHg0sGql8EcrTfHnSDDfmWTokM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=SJ0R4ABoiw5zA/IYvifxcg0waplEt50OP7lB6IscYSAyWRQ16H3nYjfg5bY7He4WOk vDlcw6+k/PdJos6VqAmm3aqdjnbM0RTsYjcYJWVGA5uySpVjj6F+2jIuk7CgoymnKWH0 +ARfSKgSolD9iTToPIE5X1lZkJO2We2V9UZiPSJnSUCiT4iCSo3amHNHBTpiHTy36yxJ vZTUpCBDl7HFGXj5ET8os02RoWcVsquRKsER2OA0NXyjjp+uBtJPVQJ6KyJlMZX8jW6g RlHRD4kaLwkU6wLO3GhKi4XGMm24/hOzjNwHRvCN/grN7R2ZzeBRHEJNMRJCtqcBFovA zV1w== X-Gm-Message-State: AKGB3mKTtnNzQFWOu3EN6xsrTe64VxqPKH/lJhpokvojNeLNBhHCjC/x bUABVhuTYrylDPz/oOBBH70YZ37foEo= X-Google-Smtp-Source: ACJfBosd7XmFrrHz3KNlx1Lruu4dQZ2hjJO45DSuUjIQ0RaCfJu8IsJOcQ2r+vQ6AbYNHnVTGfQQoQ== X-Received: by 10.84.137.106 with SMTP id 97mr18236597plm.233.1515791181241; Fri, 12 Jan 2018 13:06:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 12 Jan 2018 13:06:12 -0800 Message-Id: <20180112210613.14124-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180112210613.14124-1-richard.henderson@linaro.org> References: <20180112210613.14124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PULL 3/4] tcg/ppc: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 879885b68b..74f9b4aa34 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1524,16 +1524,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =20 /* Compensate for very large offsets. */ if (add_off >=3D 0x8000) { - /* Most target env are smaller than 32k; none are larger than 64k. - Simplify the logic here merely to offset by 0x7ff0, giving us a - range just shy of 64k. Check this assumption. */ - QEMU_BUILD_BUG_ON(offsetof(CPUArchState, - tlb_table[NB_MMU_MODES - 1][1]) - > 0x7ff0 + 0x7fff); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0)); + int low =3D (int16_t)cmp_off; + int high =3D cmp_off - low; + assert((high & 0xffff) =3D=3D 0); + assert(cmp_off - high =3D=3D (int16_t)(cmp_off - high)); + assert(add_off - high =3D=3D (int16_t)(add_off - high)); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, base, high >> 16)); base =3D TCG_REG_TMP1; - cmp_off -=3D 0x7ff0; - add_off -=3D 0x7ff0; + cmp_off -=3D high; + add_off -=3D high; } =20 /* Extraction and shifting, part 2. */ --=20 2.14.3 From nobody Fri Mar 29 12:53:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515791419625109.82858705717763; Fri, 12 Jan 2018 13:10:19 -0800 (PST) Received: from localhost ([::1]:38989 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6ag-0002pk-Ru for importer@patchew.org; Fri, 12 Jan 2018 16:10:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ea6Wv-0008Og-3f for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ea6Wu-0002oP-1b for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:25 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:45435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ea6Wt-0002nu-Rj for qemu-devel@nongnu.org; Fri, 12 Jan 2018 16:06:23 -0500 Received: by mail-pg0-x242.google.com with SMTP id c194so5319043pga.12 for ; Fri, 12 Jan 2018 13:06:23 -0800 (PST) Received: from cloudburst.twiddle.net (50-78-183-178-static.hfc.comcastbusiness.net. [50.78.183.178]) by smtp.gmail.com with ESMTPSA id t80sm20197600pgb.88.2018.01.12.13.06.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Jan 2018 13:06:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=d0OJgcwfUFpj+ZwVpj3oQFpWa4DHmM3/kAxCJICyyLs97+Egyz0tGspUwcWq2vJdK7 tn9B4hDaq2VC6R5dHKz8UVCefJt7DCg05KRN4lnhx5EnIlQSS+ASD1XPtClzmFbGsD6X NmcCbwUDL5tpb3zxHVs7h/JyHKDgG8PE9qU+Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=f5eXemkv5tW5Qxj0rzZZlDfaqD4/Ab3EUvgQUXxA+D7e8UvVv6/4JTFxJK//A2VHxe qr39UC7uTBKi4ZskFEabyxHSfWV1kRv+zwvZQfKQ8oeMZuCwzhbaPZANuqBI+RMUZIlD YWDmKuEqf84JEklOMTpactjUK+pQ7UAkPiWpif7W5iQ5tLQPSKBeAF6QOEyp/QIi8EhD /m0JTvkeR7e246MdjzrI5y7/dPTsO0hFntywQdy800/nSB1Dm4vcR3FIMKkrYHpKihA0 9ezB3WFbcOqBonBKokTaFnQ8Xr/gyWuqsS0YvlGvdg4Y42YjkM43uHkRQdUXRkHU3EWB T92A== X-Gm-Message-State: AKGB3mJCAbUnu1vtGPJv5/imYH2jmf8gjbo5dU+//Lh3xfmzifsAlzjy KdopkvEebuSvpGAGXthb0f8mxu3Ewyk= X-Google-Smtp-Source: ACJfBotVrx5v1lYvBiumzt42Z6bE+hV9ti76ckD55c8gnpV1Q5CvbzVSesKeBur+9VD40b/aq09vqg== X-Received: by 10.101.65.71 with SMTP id x7mr21935777pgp.164.1515791182572; Fri, 12 Jan 2018 13:06:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 12 Jan 2018 13:06:13 -0800 Message-Id: <20180112210613.14124-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180112210613.14124-1-richard.henderson@linaro.org> References: <20180112210613.14124-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL 4/4] tcg/ppc: Allow a 32-bit offset to the constant pool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We recently relaxed the limit of the number of opcodes that can appear in a TranslationBlock. In certain cases this has resulted in relocation overflow. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 67 ++++++++++++++++++++++++++++----------------= ---- 1 file changed, 39 insertions(+), 28 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 74f9b4aa34..86f7de5f7e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -222,33 +222,6 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, in= t insn) tcg_out32(s, insn | retrans); } =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_insn_unit *target; - tcg_insn_unit old; - - value +=3D addend; - target =3D (tcg_insn_unit *)value; - - switch (type) { - case R_PPC_REL14: - reloc_pc14(code_ptr, target); - break; - case R_PPC_REL24: - reloc_pc24(code_ptr, target); - break; - case R_PPC_ADDR16: - assert(value =3D=3D (int16_t)value); - old =3D *code_ptr; - old =3D deposit32(old, 0, 16, value); - *code_ptr =3D old; - break; - default: - tcg_abort(); - } -} - /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e) @@ -552,6 +525,43 @@ static const uint32_t tcg_to_isel[] =3D { [TCG_COND_GTU] =3D ISEL | BC_(7, CR_GT), }; =20 +static void patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_insn_unit *target; + tcg_insn_unit old; + + value +=3D addend; + target =3D (tcg_insn_unit *)value; + + switch (type) { + case R_PPC_REL14: + reloc_pc14(code_ptr, target); + break; + case R_PPC_REL24: + reloc_pc24(code_ptr, target); + break; + case R_PPC_ADDR16: + /* We are abusing this relocation type. This points to a pair + of insns, addis + load. If the displacement is small, we + can nop out the addis. */ + if (value =3D=3D (int16_t)value) { + code_ptr[0] =3D NOP; + old =3D deposit32(code_ptr[1], 0, 16, value); + code_ptr[1] =3D deposit32(old, 16, 5, TCG_REG_TB); + } else { + int16_t lo =3D value; + int hi =3D value - lo; + assert(hi + lo =3D=3D value); + code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + } + break; + default: + g_assert_not_reached(); + } +} + static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 @@ -690,7 +700,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); - tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, LD | TAI(ret, ret, 0)); return; } =20 --=20 2.14.3