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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id h80sm15740147pfj.12.2018.01.09.23.55.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jan 2018 23:55:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=NYIK9gWjTbwq9yDTzdpFXDmsXia+B0vx4db3ZCJ/XGku/Ulkg1lgAPx/XaCLxjZ1QH 7Su3BI3e58eEaO39HfstfiZ5diAit9HQK8lBXtL7jP3JaCOgbnAcCF/D18v1VxAnLnak QM2V18XJWbt+VtgUSPXAJIgjLAZJWNivj965Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=YgIKOrVAqah77eRNes5iEpaqbCoZ8kqvuK9XvInKWs/Ou8ORKN9zpqfFyG3CglLmoF +JMGUb7dg6uLt53U/cQH2wGOneFAFjPgS0tixoVBxUJsmESXRFNCVMQz0Mg4DSnRPBni uZGXTtelwJIeB9p3/iJ1Fl34VgL8VqoR4gJnxrfwDOshJuM3VmWZkeEvFou0swdMwJ9U FsOfn2TmhqwHNPP4l926Uq9epL90vsWWAeZC6juyStwgDcymQ5Pu0as2tmK08Fpj087Y qM93kHrZS0Ws0yIeorvuN+Y3CtIoCWminBkI2KgjBsXpcvQXd37kV8OMOLanye5riwdG V9qQ== X-Gm-Message-State: AKGB3mKa0MNZsATCyPycT/oAjIxDCJSKg190Dv15WsLf8lsUzblVTLEP LUviDi9K7EzFe/3R5w5YaJ2aEOzkxtQ= X-Google-Smtp-Source: ACJfBoso2sLzwiR9b6EoIfg5OVJ5SogXIC/aLobrStbHesEJP8qOZKjTtLYnFW+uPkfkbJFsm5EWMQ== X-Received: by 10.84.138.193 with SMTP id 59mr17979476plp.254.1515570951876; Tue, 09 Jan 2018 23:55:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 23:55:46 -0800 Message-Id: <20180110075547.15841-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180110075547.15841-1-richard.henderson@linaro.org> References: <20180110075547.15841-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 1/2] tcg/ppc: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 879885b68b..74f9b4aa34 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1524,16 +1524,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMe= mOp opc, =20 /* Compensate for very large offsets. */ if (add_off >=3D 0x8000) { - /* Most target env are smaller than 32k; none are larger than 64k. - Simplify the logic here merely to offset by 0x7ff0, giving us a - range just shy of 64k. Check this assumption. */ - QEMU_BUILD_BUG_ON(offsetof(CPUArchState, - tlb_table[NB_MMU_MODES - 1][1]) - > 0x7ff0 + 0x7fff); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0)); + int low =3D (int16_t)cmp_off; + int high =3D cmp_off - low; + assert((high & 0xffff) =3D=3D 0); + assert(cmp_off - high =3D=3D (int16_t)(cmp_off - high)); + assert(add_off - high =3D=3D (int16_t)(add_off - high)); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, base, high >> 16)); base =3D TCG_REG_TMP1; - cmp_off -=3D 0x7ff0; - add_off -=3D 0x7ff0; + cmp_off -=3D high; + add_off -=3D high; } =20 /* Extraction and shifting, part 2. */ --=20 2.14.3 From nobody Tue Oct 28 01:50:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515571056557205.9309633734672; Tue, 9 Jan 2018 23:57:36 -0800 (PST) Received: from localhost ([::1]:52121 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZBGR-0006gf-N7 for importer@patchew.org; Wed, 10 Jan 2018 02:57:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZBEq-0005lD-2h for qemu-devel@nongnu.org; Wed, 10 Jan 2018 02:55:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZBEo-0000gj-Tb for qemu-devel@nongnu.org; Wed, 10 Jan 2018 02:55:56 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:38981) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eZBEo-0000fz-Ny for qemu-devel@nongnu.org; Wed, 10 Jan 2018 02:55:54 -0500 Received: by mail-pl0-x241.google.com with SMTP id bi12so6826171plb.6 for ; Tue, 09 Jan 2018 23:55:54 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id h80sm15740147pfj.12.2018.01.09.23.55.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jan 2018 23:55:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=VscwwgwhfPW8W7L8zrLf6ul1+iY9IAzWrEGZrYvov/bhMsc5QcZyRVO929bf/trwWd lykzL4OZgfvANeMvh+rp9Gc0xr9pfIzDm8tgi2+6fHolL+JKghlWPztgqcU2HnVtR+VH RToOwRGLvODgWpxkXdF5aPpxV6/w/GlwWv97g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=ZkI9UvdY4PjloX3LwFhlzdaFsDbT8WOC1dr7y3bU2xEgFN2wthFM3c3VWjR0F0XA8G QMaaYVUU00D+JJIakDefX8RVWA0obwXEluDDY/HAHfiIh2Nu/bW3HMni/EJ6toE52mSo 9mCxCA0p8z/tqhVtbu2wi2cBPYWsYBlWhbvN6/boFKUuprl0Zme8VpBNJVwia+S+/XNL adDIhVF2DWg7f2lqukuzfbS+57ziI/0zsQGAdpDtcV7npYCpiB209miSdpznRmxLK/Ut bgBPHFCtOFMrMNIp6Efph+abvvzS0sxLizVy6UY5rZykmJgCMTjN0vMjvx/8dVhW+ZeC 7D6g== X-Gm-Message-State: AKGB3mKLtuq5mC55MZMDb0VsAGPrcD3+NdMV3SHtkLh8bFyjuF//NDz1 eTZarS40gDHD2OTeiOpaUrOSFqBLKLc= X-Google-Smtp-Source: ACJfBou5tphHprYtU+05BAcsnu8Wtav2xcTrgykYaLaUR9IM/13WYiniDulHwXuh2yK/qdxWFZPkpg== X-Received: by 10.159.247.136 with SMTP id e8mr12933988pls.388.1515570953322; Tue, 09 Jan 2018 23:55:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 23:55:47 -0800 Message-Id: <20180110075547.15841-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180110075547.15841-1-richard.henderson@linaro.org> References: <20180110075547.15841-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 2/2] tcg/ppc: Allow a 32-bit offset to the constant pool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We recently relaxed the limit of the number of opcodes that can appear in a TranslationBlock. In certain cases this has resulted in relocation overflow. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 67 ++++++++++++++++++++++++++++----------------= ---- 1 file changed, 39 insertions(+), 28 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 74f9b4aa34..86f7de5f7e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -222,33 +222,6 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, in= t insn) tcg_out32(s, insn | retrans); } =20 -static void patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_insn_unit *target; - tcg_insn_unit old; - - value +=3D addend; - target =3D (tcg_insn_unit *)value; - - switch (type) { - case R_PPC_REL14: - reloc_pc14(code_ptr, target); - break; - case R_PPC_REL24: - reloc_pc24(code_ptr, target); - break; - case R_PPC_ADDR16: - assert(value =3D=3D (int16_t)value); - old =3D *code_ptr; - old =3D deposit32(old, 0, 16, value); - *code_ptr =3D old; - break; - default: - tcg_abort(); - } -} - /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType typ= e) @@ -552,6 +525,43 @@ static const uint32_t tcg_to_isel[] =3D { [TCG_COND_GTU] =3D ISEL | BC_(7, CR_GT), }; =20 +static void patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_insn_unit *target; + tcg_insn_unit old; + + value +=3D addend; + target =3D (tcg_insn_unit *)value; + + switch (type) { + case R_PPC_REL14: + reloc_pc14(code_ptr, target); + break; + case R_PPC_REL24: + reloc_pc24(code_ptr, target); + break; + case R_PPC_ADDR16: + /* We are abusing this relocation type. This points to a pair + of insns, addis + load. If the displacement is small, we + can nop out the addis. */ + if (value =3D=3D (int16_t)value) { + code_ptr[0] =3D NOP; + old =3D deposit32(code_ptr[1], 0, 16, value); + code_ptr[1] =3D deposit32(old, 16, 5, TCG_REG_TB); + } else { + int16_t lo =3D value; + int hi =3D value - lo; + assert(hi + lo =3D=3D value); + code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + } + break; + default: + g_assert_not_reached(); + } +} + static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 @@ -690,7 +700,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); - tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, LD | TAI(ret, ret, 0)); return; } =20 --=20 2.14.3