From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15155128782871017.2878398374196; Tue, 9 Jan 2018 07:47:58 -0800 (PST) Received: from localhost ([::1]:58960 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw80-0003yd-4b for importer@patchew.org; Tue, 09 Jan 2018 10:47:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw5z-0002qL-BE for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw5w-0003gy-8z for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:47 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57286) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw5w-0003gT-33 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:44 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3BADCC057F87 for ; Tue, 9 Jan 2018 15:45:43 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id E445B80617; Tue, 9 Jan 2018 15:45:34 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:13 -0200 Message-Id: <20180109154519.25634-2-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 09 Jan 2018 15:45:43 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 1/7] i386: Change X86CPUDefinition::model_id to const char* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , "Dr. David Alan Gilbert" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It is valid to have a 48-character model ID on CPUID, however the definition of X86CPUDefinition::model_id is char[48], which can make the compiler drop the null terminator from the string. If a CPU model happens to have 48 bytes on model_id, "-cpu help" will print garbage and the object_property_set_str() call at x86_cpu_load_def() will read data outside the model_id array. We could increase the array size to 49, but this would mean the compiler would not issue a warning if a 49-char string is used by mistake for model_id. To make things simpler, simply change model_id to be const char*, and validate the string length using an assert() on x86_cpu_cpudef_class_init. Reported-by: "Dr. David Alan Gilbert" Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3818d72831..9f4f949899 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -754,7 +754,7 @@ struct X86CPUDefinition { int model; int stepping; FeatureWordArray features; - char model_id[48]; + const char *model_id; }; =20 static X86CPUDefinition builtin_x86_defs[] =3D { @@ -2718,6 +2718,9 @@ static void x86_cpu_cpudef_class_init(ObjectClass *oc= , void *data) X86CPUDefinition *cpudef =3D data; X86CPUClass *xcc =3D X86_CPU_CLASS(oc); =20 + /* catch mistakes instead of silently truncating model_id when too lon= g */ + assert(!cpudef->model_id || strlen(cpudef->model_id) <=3D 48); + xcc->cpu_def =3D cpudef; xcc->migration_safe =3D true; } --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515513014656271.0517863314765; Tue, 9 Jan 2018 07:50:14 -0800 (PST) Received: from localhost ([::1]:59061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYwAC-00063J-UU for importer@patchew.org; Tue, 09 Jan 2018 10:50:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw61-0002sm-AE for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw60-0003ja-DD for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36660) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw60-0003j8-44 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:48 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4012CC070E0E for ; Tue, 9 Jan 2018 15:45:47 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0A9B2811BF; Tue, 9 Jan 2018 15:45:44 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:14 -0200 Message-Id: <20180109154519.25634-3-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 09 Jan 2018 15:45:47 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 2/7] i386: Add support for SPEC_CTRL MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 3 +++ target/i386/kvm.c | 14 ++++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 62c4742703..07f47997d6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -353,6 +353,7 @@ typedef enum X86Seg { #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b +#define MSR_IA32_SPEC_CTRL 0x48 #define MSR_IA32_TSCDEADLINE 0x6e0 =20 #define FEATURE_CONTROL_LOCKED (1<<0) @@ -1125,6 +1126,8 @@ typedef struct CPUX86State { =20 uint32_t pkru; =20 + uint64_t spec_ctrl; + /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6f69e2fcfd..7afce330be 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -91,6 +91,7 @@ static bool has_msr_hv_synic; static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_xss; +static bool has_msr_spec_ctrl; =20 static bool has_msr_architectural_pmu; static uint32_t num_architectural_pmu_counters; @@ -1143,6 +1144,9 @@ static int kvm_get_supported_msrs(KVMState *s) case HV_X64_MSR_TSC_FREQUENCY: has_msr_hv_frequencies =3D true; break; + case MSR_IA32_SPEC_CTRL: + has_msr_spec_ctrl =3D true; + break; } } } @@ -1625,6 +1629,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); @@ -1633,6 +1640,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); } #endif + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. @@ -2004,6 +2012,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); + } =20 =20 if (!env->tsc_valid) { @@ -2349,6 +2360,9 @@ static int kvm_get_msrs(X86CPU *cpu) env->mtrr_var[MSR_MTRRphysIndex(index)].base =3D msrs[i].d= ata; } break; + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl =3D msrs[i].data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index df5ec359eb..361c05aedf 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -818,6 +818,25 @@ static const VMStateDescription vmstate_mcg_ext_ctl = =3D { } }; =20 +static bool spec_ctrl_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->spec_ctrl !=3D 0; +} + +static const VMStateDescription vmstate_spec_ctrl =3D { + .name =3D "cpu/spec_ctrl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D spec_ctrl_needed, + .fields =3D (VMStateField[]){ + VMSTATE_UINT64(env.spec_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -936,6 +955,7 @@ VMStateDescription vmstate_x86_cpu =3D { #ifdef TARGET_X86_64 &vmstate_pkru, #endif + &vmstate_spec_ctrl, &vmstate_mcg_ext_ctl, NULL } --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515513128132836.8723044734301; Tue, 9 Jan 2018 07:52:08 -0800 (PST) Received: from localhost ([::1]:59128 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYwC7-0007QH-DI for importer@patchew.org; Tue, 09 Jan 2018 10:52:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43126) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw65-0002x1-8E for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw64-0003lr-JB for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:53 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50574) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw64-0003lM-DV for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:52 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8287B25B89 for ; Tue, 9 Jan 2018 15:45:51 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9423861289; Tue, 9 Jan 2018 15:45:48 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:15 -0200 Message-Id: <20180109154519.25634-4-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 09 Jan 2018 15:45:51 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the feature name and a CPUID_7_0_EDX_SPEC_CTRL macro. Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + target/i386/cpu.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 07f47997d6..de387c1311 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -667,6 +667,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; =20 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Ins= tructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ +#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ =20 #define CPUID_XSAVE_XSAVEOPT (1U << 0) #define CPUID_XSAVE_XSAVEC (1U << 1) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9f4f949899..1be1642eb2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -459,7 +459,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "spec-ctrl", NULL, NULL, NULL, NULL, NULL, }, .cpuid_eax =3D 7, --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515512894828172.81718302169884; Tue, 9 Jan 2018 07:48:14 -0800 (PST) Received: from localhost ([::1]:58961 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw8M-0004Gr-2O for importer@patchew.org; Tue, 09 Jan 2018 10:48:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw6A-00031U-N0 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw69-0003ok-L5 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:58 -0500 Received: from mx1.redhat.com ([209.132.183.28]:44246) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw69-0003o6-C7 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:45:57 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7DB50C053FA7 for ; Tue, 9 Jan 2018 15:45:56 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id E43BC63139; Tue, 9 Jan 2018 15:45:52 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:16 -0200 Message-Id: <20180109154519.25634-5-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 09 Jan 2018 15:45:56 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 4/7] i386: Add FEAT_8000_0008_EBX CPUID feature word X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the new feature word and the "ibpb" feature flag. Based on a patch by Paolo Bonzini. Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 3 +++ target/i386/cpu.c | 19 ++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index de387c1311..f7df5b4f9c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -472,6 +472,7 @@ typedef enum FeatureWord { FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ + FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ @@ -669,6 +670,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ =20 +#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Predicti= on Barrier */ + #define CPUID_XSAVE_XSAVEOPT (1U << 0) #define CPUID_XSAVE_XSAVEC (1U << 1) #define CPUID_XSAVE_XGETBV1 (1U << 2) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1be1642eb2..968848a362 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -483,6 +483,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { .tcg_features =3D TCG_APM_FEATURES, .unmigratable_flags =3D CPUID_APM_INVTSC, }, + [FEAT_8000_0008_EBX] =3D { + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "ibpb", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid_eax =3D 0x80000008, + .cpuid_reg =3D R_EBX, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_XSAVE] =3D { .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", @@ -3126,7 +3142,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } else { *eax =3D cpu->phys_bits; } - *ebx =3D 0; + *ebx =3D env->features[FEAT_8000_0008_EBX]; *ecx =3D 0; *edx =3D 0; if (cs->nr_cores * cs->nr_threads > 1) { @@ -3589,6 +3605,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Erro= r **errp) x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_SVM); x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515513048894282.4443520335549; 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Tue, 9 Jan 2018 15:46:01 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id D693B8118D; Tue, 9 Jan 2018 15:45:57 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:17 -0200 Message-Id: <20180109154519.25634-6-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 09 Jan 2018 15:46:01 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 5/7] i386: Add new -IBRS versions of Intel CPU models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Jiri Denemark Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The new MSR IA32_SPEC_CTRL MSR was introduced by a recent Intel microcode updated and can be used by OSes to mitigate CVE-2017-5715. Unfortunately we can't change the existing CPU models without breaking existing setups, so users need to explicitly update their VM configuration to use the new *-IBRS CPU model if they want to expose IBRS to guests. The new CPU models are simple copies of the existing CPU models, with just CPUID_7_0_EDX_SPEC_CTRL added and model_id updated. Cc: Jiri Denemark Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 379 ++++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 378 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 968848a362..eb1bef6aa5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1081,6 +1081,31 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Core i7 9xx (Nehalem Class Core i7)", }, + { + .name =3D "Nehalem-IBRS", + .level =3D 11, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 26, + .stepping =3D 3, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core i7 9xx (Nehalem Core i7, IBRS update)", + }, { .name =3D "Westmere", .level =3D 11, @@ -1107,6 +1132,34 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, + { + .name =3D "Westmere-IBRS", + .level =3D 11, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 44, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Westmere E56xx/L56xx/X56xx (IBRS update)", + }, { .name =3D "SandyBridge", .level =3D 0xd, @@ -1138,6 +1191,39 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Xeon E312xx (Sandy Bridge)", }, + { + .name =3D "SandyBridge-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 42, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon E312xx (Sandy Bridge, IBRS update)", + }, { .name =3D "IvyBridge", .level =3D 0xd, @@ -1172,6 +1258,42 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, + { + .name =3D "IvyBridge-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 58, + .stepping =3D 9, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | + CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | + CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_ERMS, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)", + }, { .name =3D "Haswell-noTSX", .level =3D 0xd, @@ -1207,7 +1329,46 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_6_EAX_ARAT, .xlevel =3D 0x80000008, .model_id =3D "Intel Core Processor (Haswell, no TSX)", - }, { + }, + { + .name =3D "Haswell-noTSX-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 60, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core Processor (Haswell, no TSX, IBRS)", + }, + { .name =3D "Haswell", .level =3D 0xd, .vendor =3D CPUID_VENDOR_INTEL, @@ -1244,6 +1405,45 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Core Processor (Haswell)", }, + { + .name =3D "Haswell-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 60, + .stepping =3D 4, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core Processor (Haswell, IBRS)", + }, { .name =3D "Broadwell-noTSX", .level =3D 0xd, @@ -1282,6 +1482,46 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Core Processor (Broadwell, no TSX)", }, + { + .name =3D "Broadwell-noTSX-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 61, + .stepping =3D 2, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core Processor (Broadwell, no TSX, IBRS)", + }, { .name =3D "Broadwell", .level =3D 0xd, @@ -1320,6 +1560,46 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Core Processor (Broadwell)", }, + { + .name =3D "Broadwell-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 61, + .stepping =3D 2, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core Processor (Broadwell, IBRS)", + }, { .name =3D "Skylake-Client", .level =3D 0xd, @@ -1365,6 +1645,53 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Core Processor (Skylake)", }, + { + .name =3D "Skylake-Client-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 94, + .stepping =3D 3, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX, + /* Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Core Processor (Skylake, IBRS)", + }, { .name =3D "Skylake-Server", .level =3D 0xd, @@ -1413,6 +1740,56 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x80000008, .model_id =3D "Intel Xeon Processor (Skylake)", }, + { + .name =3D "Skylake-Server-IBRS", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 6, + .model =3D 85, + .stepping =3D 4, + .features[FEAT_1_EDX] =3D + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_M= CA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE= | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_SPEC_CTRL, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL, + /* Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon Processor (Skylake, IBRS)", + }, { .name =3D "Opteron_G1", .level =3D 5, --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515512906336952.3419129551322; Tue, 9 Jan 2018 07:48:26 -0800 (PST) Received: from localhost ([::1]:58962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw8X-0004Uz-H9 for importer@patchew.org; Tue, 09 Jan 2018 10:48:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw6J-000395-E5 for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw6I-0003uJ-8x for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:07 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42853) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw6I-0003th-0R for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:06 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 01F28780F9; Tue, 9 Jan 2018 15:46:05 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id 228707FB81; Tue, 9 Jan 2018 15:46:02 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:18 -0200 Message-Id: <20180109154519.25634-7-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 09 Jan 2018 15:46:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 6/7] [RFC] i386: Add EPYC-IBPB CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Jiri Denemark , Brijesh Singh , Tom Lendacky Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" RFC NOTE: More info is required to confirm if this is necessary to mitigate mitigate CVE-2017-5715 on AMD CPUs. EPYC-IBPB is a copy of the EPYC CPU model with just CPUID_8000_0008_EBX_IBPB added. Cc: Jiri Denemark Cc: Tom Lendacky Cc: Brijesh Singh Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index eb1bef6aa5..9c36f9bd44 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1964,6 +1964,52 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x8000000A, .model_id =3D "AMD EPYC Processor", }, + { + .name =3D "EPYC-IBPB", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_AMD, + .family =3D 23, + .model =3D 1, + .stepping =3D 2, + .features[FEAT_1_EDX] =3D + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUS= H | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + .features[FEAT_8000_0008_EBX] =3D + CPUID_8000_0008_EBX_IBPB, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AV= X2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED= | + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSH= OPT | + CPUID_7_0_EBX_SHA_NI, + /* Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component. + */ + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .xlevel =3D 0x8000000A, + .model_id =3D "AMD EPYC Processor (with IBPB)", + }, }; =20 typedef struct PropValue { --=20 2.14.3 From nobody Fri May 17 10:13:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515513212411244.18686130694152; Tue, 9 Jan 2018 07:53:32 -0800 (PST) Received: from localhost ([::1]:59237 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYwDP-0008Hq-99 for importer@patchew.org; Tue, 09 Jan 2018 10:53:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eYw6U-0003HP-Qr for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eYw6O-00042g-PJ for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:18 -0500 Received: from mx1.redhat.com ([209.132.183.28]:44940) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eYw6O-000428-Gz for qemu-devel@nongnu.org; Tue, 09 Jan 2018 10:46:12 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5B543C0517AC; Tue, 9 Jan 2018 15:46:11 +0000 (UTC) Received: from localhost (ovpn-116-66.gru2.redhat.com [10.97.116.66]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3846B8CCC5; Tue, 9 Jan 2018 15:46:06 +0000 (UTC) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Tue, 9 Jan 2018 13:45:19 -0200 Message-Id: <20180109154519.25634-8-ehabkost@redhat.com> In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com> References: <20180109154519.25634-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 09 Jan 2018 15:46:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Jiri Denemark , Vincent Bernat Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" RFC NOTE: we need to confirm if all Westmere/SandyBridge/IvyBridge CPUs out there support PCID, before applying this patch. RFC NOTE 2: in parallel, we are evaluating the possibility of enabling PCID on the existing Westmere/SandyBridge/IvyBridge CPU models, see https://patchew.org/QEMU/20180108205052.24385-1-vincent@bernat.im/ and https://patchew.org/QEMU/20180109070112.30806-1-vincent@bernat.im/ PCID was already available on Westmere, SandyBridge and IvyBridge, but we can't easily add it to the existing CPU models without breaking libvirt expectations about CPU model runnability (a runnable CPU model shouldn't become runnable just because of a machine-type or QEMU upgrade). However, Westmere-IBRS, SandyBridge-IBRS and IvyBridge-IBRS are new CPU models, so we can safely add PCID to them. Note that PCID is not necessary to mitigate Meltdown and/or Spectre, but it is really helpful to make performance not suffer when enabling KPTI on guest kernels. Cc: Jiri Denemark Suggested-by: Vincent Bernat Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9c36f9bd44..ad79fbb111 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1119,6 +1119,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, + /* Missing: CPUID_EXT_PCID */ .features[FEAT_1_ECX] =3D CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | @@ -1148,7 +1149,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .features[FEAT_1_ECX] =3D CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | - CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_PCID, .features[FEAT_8000_0001_EDX] =3D CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] =3D @@ -1173,6 +1174,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, + /* Missing: CPUID_EXT_PCID */ .features[FEAT_1_ECX] =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | @@ -1209,7 +1211,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | - CPUID_EXT_SSE3, + CPUID_EXT_SSE3 | CPUID_EXT_PCID, .features[FEAT_8000_0001_EDX] =3D CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, @@ -1237,6 +1239,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, + /* Missing: CPUID_EXT_PCID */ .features[FEAT_1_ECX] =3D CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | @@ -1276,7 +1279,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | - CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND | CPUID_EXT= _PCID, .features[FEAT_7_0_EBX] =3D CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS, --=20 2.14.3