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Tsirkin" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Eduardo Habkost , Marcel Apfelbaum Date: Sun, 7 Jan 2018 23:45:43 -0300 Message-Id: <20180108024558.17983-15-f4bug@amsat.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180108024558.17983-1-f4bug@amsat.org> References: <20180108024558.17983-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 14/29] piix4: add Reset Control Register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Herv=C3=A9 Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Herv=C3=A9 Poussineau --- hw/isa/piix4.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 314f7f7359..13f4eaa2dd 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -33,6 +34,10 @@ PCIDevice *piix4_dev; =20 typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; =20 #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,6 +92,34 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s =3D opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr =3D val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s =3D opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops =3D { + .read =3D piix4_rcr_read, + .write =3D piix4_rcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + static void piix4_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev =3D DEVICE(pci_dev); @@ -96,6 +129,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **e= rrp) pci_address_space_io(pci_dev), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xc= f9, + &s->rcr_mem, 1); + piix4_dev =3D pci_dev; } =20 --=20 2.15.1