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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id g10sm17740595pfe.77.2018.01.05.19.14.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Jan 2018 19:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=okhsN7PvAI2tSwB7zlFXSFL3pRM/854PTOSz2h1XJ54=; b=VdRp3OROsx/oHvGj2+JQ1PyFe5bGltXbkCjcSvb0ZS0Gi4XO4jpElo0igVCgQ8NPIa C1vhv7Yh67vhgQr3le3IuMNm3BrzXb0bVO9vSggcVfo5y7UHPB0WKHCh7oGMOPmA627E WMRBZPa1Xt2cvOWolaBtDW841gjlfaJnxjibY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=okhsN7PvAI2tSwB7zlFXSFL3pRM/854PTOSz2h1XJ54=; b=NMBR4/tCFZTsynKS+w71NlZAsBCsmDoc7Tzfuy7rsQJaZkFrADbfb/Kj69GOhdYmhy HZyJH3rnPmruEX9Cs10wHBqetdgC09hQYpTczbA9gBTN248olOdXFTEiN9mb2c3fDblc r8UYxsUucXFQxlqsKwRfzouEog/oVEzIPhim1BHsnC9UczNb4srkaWHBUmk8UGMbXA21 JRlw9YX0QoRUAOVpVTKQqAkjMo8uJZcGZVz/G0GrxeBvMZzQ87PILNVvgkFg15GAGY+T 3KwGm4VnHwwK0WbHxleEc5f0xFNtsynjJUC95QbS/7H6TqgNYS1Bn0nE3hgZOoDBD0Nr agkg== X-Gm-Message-State: AKGB3mKj2mGXygC4vEsI7KYXVYySpXjwoCdFZSx28Jt/rBXqYDCRStH4 RDPt8So8nR3z+IrBruiDEewGc9U0L+k= X-Google-Smtp-Source: ACJfBosP5qsX6IcTV4EVFwDJxH2Sm+cWb47apKePPzts/OnEPqZuajmhUNlIJpKPK5SHFXxxRVX4Uw== X-Received: by 10.99.104.200 with SMTP id d191mr661660pgc.98.1515208454935; Fri, 05 Jan 2018 19:14:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 5 Jan 2018 19:13:39 -0800 Message-Id: <20180106031346.6650-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180106031346.6650-1-richard.henderson@linaro.org> References: <20180106031346.6650-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v8 16/23] target/arm: Use vector infrastructure for aa64 dup/movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 83 +++++++++++++++++++-----------------------= ---- 1 file changed, 34 insertions(+), 49 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bc14c28e71..55a4902fc2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5846,38 +5846,24 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) * * size: encoded in imm5 (see ARM ARM LowestSetBit()) */ + static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, int imm5) { int size =3D ctz32(imm5); - int esize =3D 8 << size; - int elements =3D (is_q ? 128 : 64) / esize; - int index, i; - TCGv_i64 tmp; + int index =3D imm5 >> (size + 1); =20 if (size > 3 || (size =3D=3D 3 && !is_q)) { unallocated_encoding(s); return; } - if (!fp_access_check(s)) { return; } =20 - index =3D imm5 >> (size + 1); - - tmp =3D tcg_temp_new_i64(); - read_vec_element(s, tmp, rn, index, size); - - for (i =3D 0; i < elements; i++) { - write_vec_element(s, tmp, rd, i, size); - } - - if (!is_q) { - clear_vec_high(s, rd); - } - - tcg_temp_free_i64(tmp); + tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), + vec_reg_offset(s, rn, index, size), + is_q ? 16 : 8, vec_full_reg_size(s)); } =20 /* DUP (element, scalar) @@ -5926,9 +5912,7 @@ static void handle_simd_dupg(DisasContext *s, int is_= q, int rd, int rn, int imm5) { int size =3D ctz32(imm5); - int esize =3D 8 << size; - int elements =3D (is_q ? 128 : 64)/esize; - int i =3D 0; + uint32_t dofs, oprsz, maxsz; =20 if (size > 3 || ((size =3D=3D 3) && !is_q)) { unallocated_encoding(s); @@ -5939,12 +5923,11 @@ static void handle_simd_dupg(DisasContext *s, int i= s_q, int rd, int rn, return; } =20 - for (i =3D 0; i < elements; i++) { - write_vec_element(s, cpu_reg(s, rn), rd, i, size); - } - if (!is_q) { - clear_vec_high(s, rd); - } + dofs =3D vec_full_reg_offset(s, rd); + oprsz =3D is_q ? 16 : 8; + maxsz =3D vec_full_reg_size(s); + + tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn)); } =20 /* INS (Element) @@ -6135,7 +6118,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint3= 2_t insn) bool is_neg =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); uint64_t imm =3D 0; - TCGv_i64 tcg_rd, tcg_imm; int i; =20 if (o2 !=3D 0 || ((cmode =3D=3D 0xf) && is_neg && !is_q)) { @@ -6217,32 +6199,35 @@ static void disas_simd_mod_imm(DisasContext *s, uin= t32_t insn) imm =3D ~imm; } =20 - tcg_imm =3D tcg_const_i64(imm); - tcg_rd =3D new_tmp_a64(s); + if (!((cmode & 0x9) =3D=3D 0x1 || (cmode & 0xd) =3D=3D 0x9)) { + /* MOVI or MVNI, with MVNI negation handled above. */ + tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8, + vec_full_reg_size(s), imm); + } else { + TCGv_i64 tcg_imm =3D tcg_const_i64(imm); + TCGv_i64 tcg_rd =3D new_tmp_a64(s); =20 - for (i =3D 0; i < 2; i++) { - int foffs =3D i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, M= O_64); + for (i =3D 0; i < 2; i++) { + int foffs =3D vec_reg_offset(s, rd, i, MO_64); =20 - if (i =3D=3D 1 && !is_q) { - /* non-quad ops clear high half of vector */ - tcg_gen_movi_i64(tcg_rd, 0); - } else if ((cmode & 0x9) =3D=3D 0x1 || (cmode & 0xd) =3D=3D 0x9) { - tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); - if (is_neg) { - /* AND (BIC) */ - tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); + if (i =3D=3D 1 && !is_q) { + /* non-quad ops clear high half of vector */ + tcg_gen_movi_i64(tcg_rd, 0); } else { - /* ORR */ - tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); + tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); + if (is_neg) { + /* AND (BIC) */ + tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); + } else { + /* ORR */ + tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); + } } - } else { - /* MOVI */ - tcg_gen_mov_i64(tcg_rd, tcg_imm); + tcg_gen_st_i64(tcg_rd, cpu_env, foffs); } - tcg_gen_st_i64(tcg_rd, cpu_env, foffs); - } =20 - tcg_temp_free_i64(tcg_imm); + tcg_temp_free_i64(tcg_imm); + } } =20 /* AdvSIMD scalar copy --=20 2.14.3