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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id g10sm17740595pfe.77.2018.01.05.19.14.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Jan 2018 19:14:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ua176QlergBBCigQAYx4Bh/qGHxv4J7O/KNvAEHjYFo=; b=L58s0wVUJMjLlvaogBo3lr9qI0Cbe4Ixep23AA494V24eGdnr+NUaXG2ZNaxt3vWYV 4NfwglkvevNPjA2w0cQ1Om1vGG1T2gcw9RwlFR3821HENZYSZM3phFQ+vst00PVjtqVd 1TuuMjJ18pD7rmaFABwKwvvgQOSZeee34Ha10= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ua176QlergBBCigQAYx4Bh/qGHxv4J7O/KNvAEHjYFo=; b=eplsI7vtv9xIEINxNXpA5LiIBPONW4bVHZSLcZREhHTaOVecPe8MK8ssXYzjNTms7A VibckVIao+5xDI5IYnOpsQ5FjhjXHiMxUO/gxbXYIvLwlZIrfzp1lGY8Xx6vFpxjwcX/ SlHFffxvQCGwdGqJQCmfDqzITbgy4cihcg6NL2vaxurAND56ImhzO3r25eNfrdEu5iQm jDYyP1irTwnXC9kfR9aOOm2jZMNAkpilwkbFZxPVpy9CXAg+TMJbtIZlEqkx31d7aXJK DAfHdH1rQ+vGp0j6jyx0PV2QwGfcrRlNiu4vt8UWqvjtR9w5M7714LxDwy03si8pn/lO D1KA== X-Gm-Message-State: AKGB3mJbCsNQNZpiya4N67MWF15atssJh7uqOmdSY87aZ3QGBhc7bE8M Mam6aWg4SnXpGPZJWp9dshUWozksy2o= X-Google-Smtp-Source: ACJfBou8r5AwfMPca/tXO46axnFbsA6WE+T68HydTdM6pyPMGoX8ogG1PYzQ4gHPkOEu8n9AX+lAxw== X-Received: by 10.99.106.138 with SMTP id f132mr4156214pgc.115.1515208452099; Fri, 05 Jan 2018 19:14:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 5 Jan 2018 19:13:37 -0800 Message-Id: <20180106031346.6650-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180106031346.6650-1-richard.henderson@linaro.org> References: <20180106031346.6650-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v8 14/23] target/arm: Use vector infrastructure for aa64 add/sub/logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 207 +++++++++++++++++++++++++++++------------= ---- 1 file changed, 134 insertions(+), 73 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba94f7d045..572af456d1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" @@ -83,6 +84,10 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); =20 +/* Note that the gvec expanders operate on offsets + sizes. */ +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t); + /* initialize TCG globals. */ void a64_translate_init(void) { @@ -535,6 +540,21 @@ static inline int vec_reg_offset(DisasContext *s, int = regno, return offs; } =20 +/* Return the offset info CPUARMState of the "whole" vector register Qn. = */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return the byte size of the "whole" vector register, VL / 8. */ +static inline int vec_full_reg_size(DisasContext *s) +{ + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. + In the meantime this is just the AdvSIMD length of 128. */ + return 128 / 8; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -9048,85 +9068,125 @@ static void disas_simd_three_reg_diff(DisasContext= *s, uint32_t insn) } } =20 +static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rm); + tcg_gen_and_i64(rn, rn, rd); + tcg_gen_xor_i64(rd, rm, rn); +} + +static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rd); + tcg_gen_and_i64(rn, rn, rm); + tcg_gen_xor_i64(rd, rd, rn); +} + +static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rd); + tcg_gen_andc_i64(rn, rn, rm); + tcg_gen_xor_i64(rd, rd, rn); +} + +static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rm); + tcg_gen_and_vec(vece, rn, rn, rd); + tcg_gen_xor_vec(vece, rd, rm, rn); +} + +static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rd); + tcg_gen_and_vec(vece, rn, rn, rm); + tcg_gen_xor_vec(vece, rd, rd, rn); +} + +static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rd); + tcg_gen_andc_vec(vece, rn, rn, rm); + tcg_gen_xor_vec(vece, rd, rd, rn); +} + /* Logic op (opcode =3D=3D 3) subgroup of C3.6.16. */ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) { + static const GVecGen3 bsl_op =3D { + .fni8 =3D gen_bsl_i64, + .fniv =3D gen_bsl_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true + }; + static const GVecGen3 bit_op =3D { + .fni8 =3D gen_bit_i64, + .fniv =3D gen_bit_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true + }; + static const GVecGen3 bif_op =3D { + .fni8 =3D gen_bif_i64, + .fniv =3D gen_bif_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true + }; + int rd =3D extract32(insn, 0, 5); int rn =3D extract32(insn, 5, 5); int rm =3D extract32(insn, 16, 5); int size =3D extract32(insn, 22, 2); bool is_u =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); - TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; - int pass; + GVecGen3Fn *gvec_fn; + const GVecGen3 *gvec_op; =20 if (!fp_access_check(s)) { return; } =20 - tcg_op1 =3D tcg_temp_new_i64(); - tcg_op2 =3D tcg_temp_new_i64(); - tcg_res[0] =3D tcg_temp_new_i64(); - tcg_res[1] =3D tcg_temp_new_i64(); - - for (pass =3D 0; pass < (is_q ? 2 : 1); pass++) { - read_vec_element(s, tcg_op1, rn, pass, MO_64); - read_vec_element(s, tcg_op2, rm, pass, MO_64); - - if (!is_u) { - switch (size) { - case 0: /* AND */ - tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BIC */ - tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 2: /* ORR */ - tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 3: /* ORN */ - tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - } - } else { - if (size !=3D 0) { - /* B* ops need res loaded to operate on */ - read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - } - - switch (size) { - case 0: /* EOR */ - tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BSL bitwise select */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); - break; - case 2: /* BIT, bitwise insert if true */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - case 3: /* BIF, bitwise insert if false */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - } - } - } + switch (size + 4 * is_u) { + case 0: /* AND */ + gvec_fn =3D tcg_gen_gvec_and; + goto do_fn; + case 1: /* BIC */ + gvec_fn =3D tcg_gen_gvec_andc; + goto do_fn; + case 2: /* ORR */ + gvec_fn =3D tcg_gen_gvec_or; + goto do_fn; + case 3: /* ORN */ + gvec_fn =3D tcg_gen_gvec_orc; + goto do_fn; + case 4: /* EOR */ + gvec_fn =3D tcg_gen_gvec_xor; + goto do_fn; + do_fn: + gvec_fn(0, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + + case 5: /* BSL bitwise select */ + gvec_op =3D &bsl_op; + goto do_op; + case 6: /* BIT, bitwise insert if true */ + gvec_op =3D &bit_op; + goto do_op; + case 7: /* BIF, bitwise insert if false */ + gvec_op =3D &bif_op; + goto do_op; + do_op: + tcg_gen_gvec_3(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), gvec_op); + return; =20 - write_vec_element(s, tcg_res[0], rd, 0, MO_64); - if (!is_q) { - tcg_gen_movi_i64(tcg_res[1], 0); + default: + g_assert_not_reached(); } - write_vec_element(s, tcg_res[1], rd, 1, MO_64); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res[0]); - tcg_temp_free_i64(tcg_res[1]); } =20 /* Helper functions for 32 bit comparisons */ @@ -9387,6 +9447,7 @@ static void disas_simd_3same_int(DisasContext *s, uin= t32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); int pass; + GVecGen3Fn *gvec_op; =20 switch (opcode) { case 0x13: /* MUL, PMUL */ @@ -9426,6 +9487,16 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) return; } =20 + switch (opcode) { + case 0x10: /* ADD, SUB */ + gvec_op =3D u ? tcg_gen_gvec_sub : tcg_gen_gvec_add; + gvec_op(size, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + if (size =3D=3D 3) { assert(is_q); for (pass =3D 0; pass < 2; pass++) { @@ -9598,16 +9669,6 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) genfn =3D fns[size][u]; break; } - case 0x10: /* ADD, SUB */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x11: /* CMTST, CMEQ */ { static NeonGenTwoOpFn * const fns[3][2] =3D { --=20 2.14.3