From nobody Tue Oct 28 04:32:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1515084686894419.47330638225674; Thu, 4 Jan 2018 08:51:26 -0800 (PST) Received: from localhost ([::1]:50025 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eX8jm-0007Ri-4P for importer@patchew.org; Thu, 04 Jan 2018 11:51:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eX8bf-0007d2-1m for qemu-devel@nongnu.org; Thu, 04 Jan 2018 11:43:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eX8bc-0003ek-QU for qemu-devel@nongnu.org; Thu, 04 Jan 2018 11:43:03 -0500 Received: from mout.kundenserver.de ([212.227.126.133]:57770) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eX8bc-0003bm-90 for qemu-devel@nongnu.org; Thu, 04 Jan 2018 11:43:00 -0500 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003 [212.227.15.167]) with ESMTPSA (Nemesis) id 0Lfnn4-1fGvt22Cq2-00pLjh; Thu, 04 Jan 2018 17:42:58 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 4 Jan 2018 17:42:48 +0100 Message-Id: <20180104164251.26494-15-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180104164251.26494-1-laurent@vivier.eu> References: <20180104164251.26494-1-laurent@vivier.eu> X-Provags-ID: V03:K0:n0RlLXjQNjRJhePxcQCU6u+Y60Fi7cHNFn1ZuijIsokjRYdxdKG xyGOHpbvJGdiGnNkK8wCF1Bajllo/d54q0gi3nArNY5T5SaapF60Nc+7zmxaDmPqfbV0J0w vavHSIUiXbItbfeB644LILVYAdsAD2jOR/JXhLaW6CbAaLvljTqiKQY9qQeUMpK9Ep/XkIP OQpBgWFOaAeW32y+QqBcA== X-UI-Out-Filterresults: notjunk:1;V01:K0:+5Ff4kl1ea4=:tB3ZgAlH3hGLeK7tGhOEe5 ZOKTYbBikMCLWrnEEV5kFlTqz3uQxYHJclLvnKbBuuxOKdKrKy0y4GbS/C4m12QAcebVdKPdq YUq7woUW3uv0foJ5mghVkDEh34V+IDtb2u8x9zpTYHj6MLpHs2rrztrimB/Ur2z5gn0n/0Tes r6f9g2a0ck/juygWIUOarDt91l9SDLQh6quKxnJdBo2Wz5SZp0XEHUh4E5pkRMenWHQxxaze5 Kgb+tJ/uteTl/F14maoSDX4leBOTldt9A033Lc/jfTFdz50MfqwPeJtWiOj0fAHAa+LIOIYw9 K2LsNtxj35KBMbIc/4wwL+xCaWqVpecQPxsWIWs7IAdMhkIctV4EBQU1zIZXf68ylSTk6VqUU wP93VxWJ8SRqJT54JbkC/TdZXr4t4oZzPtyJfAoLuQkxI9NWR0kshst6g0KOk+1R8tlLxNArc AKG8P36rDxM3+fv86w1D9JFWAGorKcBY9M3RTzq3cQlk2KE18gEO5gVIb+zF0BXnRgWxhYH16 q7K9oHnwUptPn3xI9JHFnkWLpxeQXdGYO0IQGRbHL+rMi4gcelwq2FbP8Zm43JpcDh9PhlaWl KOh/Z4JA1eRamb47Xq/6fohKYN36JbkzMH19Bv+hPj8s18xA2r9HOBjfvBNyFWxqrksxY0qbn U80b/DAIfjPUKpT8MEX44rnOxZChqI8FKEJP4cB3nWlZrIza4n2IzvcEZr0g5IHUuSXGBv9vi IhSz/A5Z3sTOnItIdKrDzIYs8MTZ0ymBTeOMXiMVNmvm23IMqdpWzLwjvy8= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.133 Subject: [Qemu-devel] [PULL 14/17] target/m68k: add 680x0 "move to SR" instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some cleanup, and allows SR to be moved from any addressing mode. Previous code was wrong for coldfire: coldfire also allows to use addressing mode to set SR/CCR. It only supports Data register to get SR/CCR (move from) Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20180104012913.30763-15-laurent@vivier.eu> --- target/m68k/translate.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1f867a4f7a..8f23cade04 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2162,27 +2162,34 @@ static void gen_set_sr_im(DisasContext *s, uint16_t= val, int ccr_only) tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); } else { - gen_helper_set_sr(cpu_env, tcg_const_i32(val)); + TCGv sr =3D tcg_const_i32(val); + gen_helper_set_sr(cpu_env, sr); + tcg_temp_free(sr); } set_cc_op(s, CC_OP_FLAGS); } =20 -static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, - int ccr_only) +static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) { - if ((insn & 0x38) =3D=3D 0) { - if (ccr_only) { - gen_helper_set_ccr(cpu_env, DREG(insn, 0)); - } else { - gen_helper_set_sr(cpu_env, DREG(insn, 0)); - } - set_cc_op(s, CC_OP_FLAGS); - } else if ((insn & 0x3f) =3D=3D 0x3c) { + if (ccr_only) { + gen_helper_set_ccr(cpu_env, val); + } else { + gen_helper_set_sr(cpu_env, val); + } + set_cc_op(s, CC_OP_FLAGS); +} + +static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t in= sn, + bool ccr_only) +{ + if ((insn & 0x3f) =3D=3D 0x3c) { uint16_t val; val =3D read_im16(env, s); gen_set_sr_im(s, val, ccr_only); } else { - disas_undef(env, s, insn); + TCGv src; + SRC_EA(env, src, OS_WORD, 0, NULL); + gen_set_sr(s, src, ccr_only); } } =20 @@ -2557,7 +2564,7 @@ DISAS_INSN(neg) =20 DISAS_INSN(move_to_ccr) { - gen_set_sr(env, s, insn, 1); + gen_move_to_sr(env, s, insn, true); } =20 DISAS_INSN(not) @@ -4409,7 +4416,7 @@ DISAS_INSN(move_to_sr) gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); return; } - gen_set_sr(env, s, insn, 0); + gen_move_to_sr(env, s, insn, false); gen_lookup_tb(s); } =20 @@ -5556,9 +5563,8 @@ void register_m68k_insns (CPUM68KState *env) BASE(move_to_ccr, 44c0, ffc0); INSN(not, 4680, fff8, CF_ISA_A); INSN(not, 4600, ff00, M68000); - INSN(undef, 46c0, ffc0, M68000); #if defined(CONFIG_SOFTMMU) - INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); + BASE(move_to_sr, 46c0, ffc0); #endif INSN(nbcd, 4800, ffc0, M68000); INSN(linkl, 4808, fff8, M68000); --=20 2.14.3