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X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v4 17/17] sdhci: add a "dma-memory" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" , Peter Maydell , Eduardo Habkost , Andrey Smirnov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add a dma property allowing machine creation to provide the address-space sdhci dma operates on. [based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2016.1] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 36 +++++++++++++++++++++++------------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 9436375b1e..2aea20f1d8 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -41,6 +41,8 @@ typedef struct SDHCIState { /*< public >*/ SDBus sdbus; MemoryRegion iomem; + MemoryRegion *dma_mr; + AddressSpace dma_as; =20 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ QEMUTimer *transfer_timer; diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 97129e178e..a5e63dbd56 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -502,7 +502,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState= *s) s->blkcnt--; } } - dma_memory_write(&address_space_memory, s->sdmasysad, + dma_memory_write(&s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], s->data_count - begin= ); s->sdmasysad +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { @@ -524,7 +524,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState= *s) s->data_count =3D block_size; boundary_count -=3D block_size - begin; } - dma_memory_read(&address_space_memory, s->sdmasysad, + dma_memory_read(&s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], s->data_count - begin); s->sdmasysad +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { @@ -562,11 +562,9 @@ static void sdhci_sdma_transfer_single_block(SDHCIStat= e *s) for (n =3D 0; n < datacnt; n++) { s->fifo_buffer[n] =3D sdbus_read_data(&s->sdbus); } - dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buff= er, - datacnt); + dma_memory_write(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt= ); } else { - dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffe= r, - datacnt); + dma_memory_read(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); for (n =3D 0; n < datacnt; n++) { sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); } @@ -590,7 +588,7 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) hwaddr entry_addr =3D (hwaddr)s->admasysaddr; switch (SDHC_DMA_TYPE(s->hostctl)) { case SDHC_CTRL_ADMA2_32: - dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adm= a2, + dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma2, sizeof(adma2)); adma2 =3D le64_to_cpu(adma2); /* The spec does not specify endianness of descriptor table. @@ -602,7 +600,7 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) dscr->incr =3D 8; break; case SDHC_CTRL_ADMA1_32: - dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adm= a1, + dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma1, sizeof(adma1)); adma1 =3D le32_to_cpu(adma1); dscr->addr =3D (hwaddr)(adma1 & 0xFFFFF000); @@ -615,12 +613,12 @@ static void get_adma_description(SDHCIState *s, ADMAD= escr *dscr) } break; case SDHC_CTRL_ADMA2_64: - dma_memory_read(&address_space_memory, entry_addr, + dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)(&dscr->attr), 1); - dma_memory_read(&address_space_memory, entry_addr + 2, + dma_memory_read(&s->dma_as, entry_addr + 2, (uint8_t *)(&dscr->length), 2); dscr->length =3D le16_to_cpu(dscr->length); - dma_memory_read(&address_space_memory, entry_addr + 4, + dma_memory_read(&s->dma_as, entry_addr + 4, (uint8_t *)(&dscr->addr), 8); dscr->attr =3D le64_to_cpu(dscr->attr); dscr->attr &=3D 0xfffffff8; @@ -679,7 +677,7 @@ static void sdhci_do_adma(SDHCIState *s) s->data_count =3D block_size; length -=3D block_size - begin; } - dma_memory_write(&address_space_memory, dscr.addr, + dma_memory_write(&s->dma_as, dscr.addr, &s->fifo_buffer[begin], s->data_count - begin); dscr.addr +=3D s->data_count - begin; @@ -703,7 +701,7 @@ static void sdhci_do_adma(SDHCIState *s) s->data_count =3D block_size; length -=3D block_size - begin; } - dma_memory_read(&address_space_memory, dscr.addr, + dma_memory_read(&s->dma_as, dscr.addr, &s->fifo_buffer[begin], s->data_count - begin); dscr.addr +=3D s->data_count - begin; @@ -1198,10 +1196,20 @@ static void sdhci_realizefn(SDHCIState *s, Error **= errp) =20 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci= ", SDHC_REGISTERS_MAP_SIZE); + + /* use system_memory() if property "dma-memory" not set */ + address_space_init(&s->dma_as, + s->dma_mr ? s->dma_mr : get_system_memory(), + "sdhci-dma"); } =20 static void sdhci_unrealizefn(SDHCIState *s, Error **errp) { + if (s->dma_mr) { + address_space_destroy(&s->dma_as); + object_unparent(OBJECT(&s->dma_mr)); + } + g_free(s->fifo_buffer); /* This function is expected to be called only once for each class: * - SysBus: via DeviceClass->unrealize(), @@ -1288,6 +1296,8 @@ static Property sdhci_properties[] =3D { DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0), DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_qu= irk, false), + DEFINE_PROP_LINK("dma-memory", SDHCIState, dma_mr, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.15.1