From nobody Tue Oct 28 12:37:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151495377700472.90253418231498; Tue, 2 Jan 2018 20:29:37 -0800 (PST) Received: from localhost ([::1]:38631 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWagK-0005Yf-1N for importer@patchew.org; Tue, 02 Jan 2018 23:29:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWabc-0001C7-3S for qemu-devel@nongnu.org; Tue, 02 Jan 2018 23:24:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eWaba-0001zA-HK for qemu-devel@nongnu.org; Tue, 02 Jan 2018 23:24:44 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:40593) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eWaba-0001uv-5F; Tue, 02 Jan 2018 23:24:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zBHrj2sdbz9t3w; Wed, 3 Jan 2018 15:24:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1514953477; bh=l+3loFxoTSOlUwoGP0gm9UV1DaD8PIrHUCFLUxiZfL4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PlKf6YurZce7vpq59rl1BLcACJNB14w9R8rFGm5vWC3VjgcfJ7MRJ3jRlr91IWG7X DwP79U9rhMNuHvimGWboBeescW8TdVtUn+vAxEKe48HZy9K9sGcvqC6aJhTx87c6uh WjwpM6ocT7Z6ukDGvMl2GHTjhN13w+K4vnnmjHOc= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 3 Jan 2018 15:24:19 +1100 Message-Id: <20180103042419.14520-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180103042419.14520-1-david@gibson.dropbear.id.au> References: <20180103042419.14520-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 15/15] target/ppc: more use of the PPC_*() macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater Also introduce utilities to manipulate bitmasks (originaly from OPAL) which be will be used in the model of the XIVE interrupt controller. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_lpc.c | 10 ++++----- target/ppc/cpu.h | 56 ++++++++++++++++++++++++++++++---------------= ---- target/ppc/int_helper.c | 2 +- 3 files changed, 40 insertions(+), 28 deletions(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index b777b78e18..c42b4a8f6c 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -146,13 +146,13 @@ static bool opb_write(PnvLpcController *lpc, uint32_t= addr, uint8_t *data, return success; } =20 -#define ECCB_CTL_READ (1ull << (63 - 15)) +#define ECCB_CTL_READ PPC_BIT(15) #define ECCB_CTL_SZ_LSH (63 - 7) -#define ECCB_CTL_SZ_MASK (0xfull << ECCB_CTL_SZ_LSH) -#define ECCB_CTL_ADDR_MASK 0xffffffffu; +#define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7) +#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63) =20 -#define ECCB_STAT_OP_DONE (1ull << (63 - 52)) -#define ECCB_STAT_OP_ERR (1ull << (63 - 52)) +#define ECCB_STAT_OP_DONE PPC_BIT(52) +#define ECCB_STAT_OP_ERR PPC_BIT(52) #define ECCB_STAT_RD_DATA_LSH (63 - 37) #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 370b05e76e..a5e49f23e9 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -93,6 +93,19 @@ #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ PPC_BIT32(bs)) +#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(= bs)) + +#if HOST_LONG_BITS =3D=3D 32 +# define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1) +#elif HOST_LONG_BITS =3D=3D 64 +# define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1) +#else +# error Unknown sizeof long +#endif + +#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) +#define SETFIELD(m, v, val) \ + (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) =20 /*************************************************************************= ****/ /* Exception vectors definitions = */ @@ -2349,32 +2362,31 @@ enum { =20 /* Processor Compatibility mask (PCR) */ enum { - PCR_COMPAT_2_05 =3D 1ull << (63-62), - PCR_COMPAT_2_06 =3D 1ull << (63-61), - PCR_COMPAT_2_07 =3D 1ull << (63-60), - PCR_COMPAT_3_00 =3D 1ull << (63-59), - PCR_VEC_DIS =3D 1ull << (63-0), /* Vec. disable (bit NA since = POWER8) */ - PCR_VSX_DIS =3D 1ull << (63-1), /* VSX disable (bit NA since P= OWER8) */ - PCR_TM_DIS =3D 1ull << (63-2), /* Trans. memory disable (POWE= R8) */ + PCR_COMPAT_2_05 =3D PPC_BIT(62), + PCR_COMPAT_2_06 =3D PPC_BIT(61), + PCR_COMPAT_2_07 =3D PPC_BIT(60), + PCR_COMPAT_3_00 =3D PPC_BIT(59), + PCR_VEC_DIS =3D PPC_BIT(0), /* Vec. disable (bit NA since POWE= R8) */ + PCR_VSX_DIS =3D PPC_BIT(1), /* VSX disable (bit NA since POWER= 8) */ + PCR_TM_DIS =3D PPC_BIT(2), /* Trans. memory disable (POWER8) = */ }; =20 /* HMER/HMEER */ enum { - HMER_MALFUNCTION_ALERT =3D 1ull << (63 - 0), - HMER_PROC_RECV_DONE =3D 1ull << (63 - 2), - HMER_PROC_RECV_ERROR_MASKED =3D 1ull << (63 - 3), - HMER_TFAC_ERROR =3D 1ull << (63 - 4), - HMER_TFMR_PARITY_ERROR =3D 1ull << (63 - 5), - HMER_XSCOM_FAIL =3D 1ull << (63 - 8), - HMER_XSCOM_DONE =3D 1ull << (63 - 9), - HMER_PROC_RECV_AGAIN =3D 1ull << (63 - 11), - HMER_WARN_RISE =3D 1ull << (63 - 14), - HMER_WARN_FALL =3D 1ull << (63 - 15), - HMER_SCOM_FIR_HMI =3D 1ull << (63 - 16), - HMER_TRIG_FIR_HMI =3D 1ull << (63 - 17), - HMER_HYP_RESOURCE_ERR =3D 1ull << (63 - 20), - HMER_XSCOM_STATUS_MASK =3D 7ull << (63 - 23), - HMER_XSCOM_STATUS_LSH =3D (63 - 23), + HMER_MALFUNCTION_ALERT =3D PPC_BIT(0), + HMER_PROC_RECV_DONE =3D PPC_BIT(2), + HMER_PROC_RECV_ERROR_MASKED =3D PPC_BIT(3), + HMER_TFAC_ERROR =3D PPC_BIT(4), + HMER_TFMR_PARITY_ERROR =3D PPC_BIT(5), + HMER_XSCOM_FAIL =3D PPC_BIT(8), + HMER_XSCOM_DONE =3D PPC_BIT(9), + HMER_PROC_RECV_AGAIN =3D PPC_BIT(11), + HMER_WARN_RISE =3D PPC_BIT(14), + HMER_WARN_FALL =3D PPC_BIT(15), + HMER_SCOM_FIR_HMI =3D PPC_BIT(16), + HMER_TRIG_FIR_HMI =3D PPC_BIT(17), + HMER_HYP_RESOURCE_ERR =3D PPC_BIT(20), + HMER_XSCOM_STATUS_MASK =3D PPC_BITMASK(21, 23), }; =20 /* Alternate Interrupt Location (AIL) */ diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 1c013a0ee3..3a50f1e1b7 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -183,7 +183,7 @@ uint64_t helper_bpermd(uint64_t rs, uint64_t rb) for (i =3D 0; i < 8; i++) { int index =3D (rs >> (i*8)) & 0xFF; if (index < 64) { - if (rb & (1ull << (63-index))) { + if (rb & PPC_BIT(index)) { ra |=3D 1 << i; } } --=20 2.14.3