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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id q68sm71240492pfb.1.2017.12.29.11.31.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Dec 2017 11:31:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=khE8rSygkJxKJIlL4o6HtdlZEHgkFCJk+nQSZzTHpP0=; b=bs3r3BlE0nNoHEBBexAqBbH4mJBTMUUjjHBnR29nB1MNrwHI7V1devXXqtrfr1gI5U s+AnhaLE5+JsASbBGOHE4rUOEquprSRtnBiiZCXfEY/qpEVJMDPBqD1TDrs0uQeRhpVz gUY4jdeArnx1QV06tDCdhAHI3gGQIAe6BbIiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=khE8rSygkJxKJIlL4o6HtdlZEHgkFCJk+nQSZzTHpP0=; b=eTsOOWDaMr49GW4ue/vcuSB0o5H6WkPjmKSTqJWMi5GoNd66drjQjAFNXV8C4v3xW7 pE+0pnwkdJqBVDOZGl2V/mZDxNfm/YyujF8ZwD+wrqW2FNtE77bRobo114QljQoc367s 6/HUN0A4las893NgY2AHbWD5eDTV0MjFSc8Ol9DTH+wLwb/Mp+5M/esOksfWO7nYTQai KgX8X9UX/VX9/sFCrjiE5pzOWVdRZqlKSe+fgZEF5W9bbHgPxsIiN9nNIgYfDuxGhb1U 6laAn+w3KFMNklx7neeW0zsSXQ1m1kJwIxaaY3tj3K30q+1483Chav8itAf0IOQdg1/R N8jw== X-Gm-Message-State: AKGB3mL7U0ZZaENGndxO4vStcuHCmV/udWcPBaPypN05uFwC85y8kmyZ HZ6gNlDpoAHVRf973SyL2W/y32NXMwg= X-Google-Smtp-Source: ACJfBoszcjXVmTHdNWlpmMwHd7tYAx6aejYT6DddAKIgHY2jU6gGDzKQtikCZJ/22i6Tp0z/l8iHQQ== X-Received: by 10.84.245.138 with SMTP id j10mr35937974pll.281.1514575877381; Fri, 29 Dec 2017 11:31:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 29 Dec 2017 11:31:06 -0800 Message-Id: <20171229193113.11753-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229193113.11753-1-richard.henderson@linaro.org> References: <20171229193113.11753-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 1/8] target/*helper: don't check retaddr before calling cpu_restore_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Benn=C3=A9e [rth: Fixed up comment indentation. Added second hunk to script to combine cpu_restore_state and cpu_loop_exit.] Signed-off-by: Richard Henderson --- target/alpha/mem_helper.c | 13 +++---------- target/arm/op_helper.c | 18 ++++++------------ target/i386/svm_helper.c | 4 +--- target/lm32/op_helper.c | 7 ++----- target/m68k/op_helper.c | 7 ++----- target/microblaze/op_helper.c | 7 ++----- target/moxie/helper.c | 4 +--- target/nios2/mmu.c | 7 ++----- target/openrisc/mmu_helper.c | 6 +----- target/tricore/op_helper.c | 13 +++---------- target/unicore32/op_helper.c | 7 ++----- scripts/coccinelle/cpu_restore_state.cocci | 19 +++++++++++++++++++ 12 files changed, 44 insertions(+), 68 deletions(-) create mode 100644 scripts/coccinelle/cpu_restore_state.cocci diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 3c06baa93a..430eea470b 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -34,9 +34,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr ad= dr, uint64_t pc; uint32_t insn; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -58,9 +56,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; @@ -80,11 +76,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D alpha_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret !=3D 0)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } /* Exception index and error code are already set */ - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, retaddr); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c2bb4f3a43..b36206343d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -182,10 +182,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, if (unlikely(ret)) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } @@ -199,10 +197,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 fi.type =3D ARMFault_Alignment; deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); @@ -221,10 +217,8 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 /* The EA bit in syndromes and fault status registers is an * IMPDEF classification of external aborts. ARM implementations diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index f479239875..303106981c 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -584,9 +584,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, { CPUState *cs =3D CPU(x86_env_get_cpu(env)); =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 2177c8ad12..30f670eee8 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -151,11 +151,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, =20 ret =3D lm32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 63089511cb..78bfb9f0cc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } =20 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1e07e21c1c..4cf51568df 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -40,11 +40,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 330299f5a7..2ecee89f11 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -36,9 +36,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 ret =3D moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index fe9298af50..0cd8647510 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -42,11 +42,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } =20 diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a44d0aa51a..a3e182c42d 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -33,12 +33,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); =20 if (ret) { - if (retaddr) { - /* now we have a real cpu fault. */ - cpu_restore_state(cs, retaddr); - } /* Raise Exception. */ - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 7af202c8c0..40ed229486 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,9 +31,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint3= 2_t class, int tin, { CPUState *cs =3D CPU(tricore_env_get_cpu(env)); /* in case we come from a helper-call we need to restore the PC */ - if (pc) { - cpu_restore_state(cs, pc); - } + cpu_restore_state(cs, pc); =20 /* Tin is loaded into d[15] */ env->gpr_d[15] =3D tin; @@ -2804,13 +2802,8 @@ static inline void QEMU_NORETURN do_raise_exception_= err(CPUTriCoreState *env, CPUState *cs =3D CPU(tricore_env_get_cpu(env)); cs->exception_index =3D exception; env->error_code =3D error_code; - - if (pc) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, pc); - } - - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, pc); } =20 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 0872c29faa..8788642a7f 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -251,11 +251,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, =20 ret =3D uc32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/scripts/coccinelle/cpu_restore_state.cocci b/scripts/coccinell= e/cpu_restore_state.cocci new file mode 100644 index 0000000000..61bc749d14 --- /dev/null +++ b/scripts/coccinelle/cpu_restore_state.cocci @@ -0,0 +1,19 @@ +// Remove unneeded tests before calling cpu_restore_state +// +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file ./scripts/coccinelle/cpu_restore_state.cocci \ +// --keep-comments --in-place --use-gitgrep --dir target +@@ +expression A; +expression C; +@@ +-if (A) { + cpu_restore_state(C, A); +-} +@@ +expression A; +expression C; +@@ +- cpu_restore_state(C, A); +- cpu_loop_exit(C); ++ cpu_loop_exit_restore(C, A); --=20 2.14.3