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Iglesias" , Peter Maydell , Andrey Smirnov Date: Fri, 29 Dec 2017 14:49:00 -0300 Message-Id: <20171229174933.1781-10-f4bug@amsat.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171229174933.1781-1-f4bug@amsat.org> References: <20171229174933.1781-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v3 09/42] sdhci: convert the DPRINT() calls into trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 zero-initialize ADMADescr 'dscr' in sdhci_do_adma() to avoid: hw/sd/sdhci.c: In function =E2=80=98sdhci_do_adma=E2=80=99: hw/sd/sdhci.c:714:29: error: =E2=80=98dscr.addr=E2=80=99 may be used unin= itialized in this function [-Werror=3Dmaybe-uninitialized] trace_sdhci_adma("link", s->admasysaddr); ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- hw/sd/sdhci.c | 89 ++++++++++++++++++--------------------------------= ---- hw/sd/trace-events | 14 +++++++++ 2 files changed, 44 insertions(+), 59 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index afb3a794ec..acd5aa1e19 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -33,30 +33,7 @@ #include "sdhci-internal.h" #include "qapi/error.h" #include "qemu/log.h" - -/* host controller debug messages */ -#ifndef SDHC_DEBUG -#define SDHC_DEBUG 0 -#endif - -#define DPRINT_L1(fmt, args...) \ - do { \ - if (SDHC_DEBUG) { \ - fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ - } \ - } while (0) -#define DPRINT_L2(fmt, args...) \ - do { \ - if (SDHC_DEBUG > 1) { \ - fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ - } \ - } while (0) -#define ERRPRINT(fmt, args...) \ - do { \ - if (SDHC_DEBUG) { \ - fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ - } \ - } while (0) +#include "trace.h" =20 #define TYPE_SDHCI_BUS "sdhci-bus" #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) @@ -155,8 +132,8 @@ static void sdhci_raise_insertion_irq(void *opaque) static void sdhci_set_inserted(DeviceState *dev, bool level) { SDHCIState *s =3D (SDHCIState *)dev; - DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); =20 + trace_sdhci_set_inserted(level ? "insert" : "eject"); if ((s->norintsts & SDHC_NIS_REMOVE) && level) { /* Give target some time to notice card ejection */ timer_mod(s->insert_timer, @@ -238,7 +215,8 @@ static void sdhci_send_command(SDHCIState *s) s->acmd12errsts =3D 0; request.cmd =3D s->cmdreg >> 8; request.arg =3D s->argument; - DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); + + trace_sdhci_send_command(request.cmd, request.arg); rlen =3D sdbus_do_command(&s->sdbus, &request, response); =20 if (s->cmdreg & SDHC_CMD_RESPONSE) { @@ -246,7 +224,7 @@ static void sdhci_send_command(SDHCIState *s) s->rspreg[0] =3D (response[0] << 24) | (response[1] << 16) | (response[2] << 8) | response[3]; s->rspreg[1] =3D s->rspreg[2] =3D s->rspreg[3] =3D 0; - DPRINT_L1("Response: RSPREG[31..0]=3D0x%08x\n", s->rspreg[0]); + trace_sdhci_response4(s->rspreg[0]); } else if (rlen =3D=3D 16) { s->rspreg[0] =3D (response[11] << 24) | (response[12] << 16) | (response[13] << 8) | response[14]; @@ -256,11 +234,10 @@ static void sdhci_send_command(SDHCIState *s) (response[5] << 8) | response[6]; s->rspreg[3] =3D (response[0] << 16) | (response[1] << 8) | response[2]; - DPRINT_L1("Response received:\n RSPREG[127..96]=3D0x%08x, RSPR= EG[95.." - "64]=3D0x%08x,\n RSPREG[63..32]=3D0x%08x, RSPREG[31..0]= =3D0x%08x\n", - s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); + trace_sdhci_response16(s->rspreg[3], s->rspreg[2], + s->rspreg[1], s->rspreg[0]); } else { - ERRPRINT("Timeout waiting for command response\n"); + trace_sdhci_error("timeout waiting for command response"); if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { s->errintsts |=3D SDHC_EIS_CMDTIMEOUT; s->norintsts |=3D SDHC_NIS_ERR; @@ -294,7 +271,7 @@ static void sdhci_end_transfer(SDHCIState *s) =20 request.cmd =3D 0x0C; request.arg =3D 0; - DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request= .arg); + trace_sdhci_end_transfer(request.cmd, request.arg); sdbus_do_command(&s->sdbus, &request, response); /* Auto CMD12 response goes to the upper Response register */ s->rspreg[3] =3D (response[0] << 24) | (response[1] << 16) | @@ -363,7 +340,7 @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsi= gned size) =20 /* first check that a valid data exists in host controller input buffe= r */ if ((s->prnsts & SDHC_DATA_AVAILABLE) =3D=3D 0) { - ERRPRINT("Trying to read from empty buffer\n"); + trace_sdhci_error("read from empty buffer"); return 0; } =20 @@ -372,8 +349,7 @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsi= gned size) s->data_count++; /* check if we've read all valid data (blksize bytes) from buffer = */ if ((s->data_count) >=3D (s->blksize & 0x0fff)) { - DPRINT_L2("All %u bytes of data have been read from input buff= er\n", - s->data_count); + trace_sdhci_read_dataport(s->data_count); s->prnsts &=3D ~SDHC_DATA_AVAILABLE; /* no more data in a buff= er */ s->data_count =3D 0; /* next buff read must start at position= [0] */ =20 @@ -456,7 +432,7 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_= t value, unsigned size) =20 /* Check that there is free space left in a buffer */ if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { - ERRPRINT("Can't write to data buffer: buffer full\n"); + trace_sdhci_error("Can't write to data buffer: buffer full"); return; } =20 @@ -465,8 +441,7 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_= t value, unsigned size) s->data_count++; value >>=3D 8; if (s->data_count >=3D (s->blksize & 0x0fff)) { - DPRINT_L2("write buffer filled with %u bytes of data\n", - s->data_count); + trace_sdhci_write_dataport(s->data_count); s->data_count =3D 0; s->prnsts &=3D ~SDHC_SPACE_AVAILABLE; if (s->prnsts & SDHC_DOING_WRITE) { @@ -654,15 +629,14 @@ static void sdhci_do_adma(SDHCIState *s) { unsigned int n, begin, length; const uint16_t block_size =3D s->blksize & 0x0fff; - ADMADescr dscr; + ADMADescr dscr =3D {}; int i; =20 for (i =3D 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { s->admaerr &=3D ~SDHC_ADMAERR_LENGTH_MISMATCH; =20 get_adma_description(s, &dscr); - DPRINT_L2("ADMA loop: addr=3D" TARGET_FMT_plx ", len=3D%d, attr=3D= %x\n", - dscr.addr, dscr.length, dscr.attr); + trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); =20 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) =3D=3D 0) { /* Indicate that error occurred in ST_FDS state */ @@ -745,8 +719,7 @@ static void sdhci_do_adma(SDHCIState *s) break; case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ s->admasysaddr =3D dscr.addr; - DPRINT_L1("ADMA link: admasysaddr=3D0x%" PRIx64 "\n", - s->admasysaddr); + trace_sdhci_adma("link", s->admasysaddr); break; default: s->admasysaddr +=3D dscr.incr; @@ -754,8 +727,7 @@ static void sdhci_do_adma(SDHCIState *s) } =20 if (dscr.attr & SDHC_ADMA_ATTR_INT) { - DPRINT_L1("ADMA interrupt: admasysaddr=3D0x%" PRIx64 "\n", - s->admasysaddr); + trace_sdhci_adma("interrupt", s->admasysaddr); if (s->norintstsen & SDHC_NISEN_DMA) { s->norintsts |=3D SDHC_NIS_DMA; } @@ -766,15 +738,15 @@ static void sdhci_do_adma(SDHCIState *s) /* ADMA transfer terminates if blkcnt =3D=3D 0 or by END attribute= */ if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt =3D=3D 0)) || (dscr.attr & SDHC_ADMA_ATTR_E= ND)) { - DPRINT_L2("ADMA transfer completed\n"); + trace_sdhci_adma_transfer_completed(); if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && s->blkcnt !=3D 0)) { - ERRPRINT("SD/MMC host ADMA length mismatch\n"); + trace_sdhci_error("SD/MMC host ADMA length mismatch"); s->admaerr |=3D SDHC_ADMAERR_LENGTH_MISMATCH | SDHC_ADMAERR_STATE_ST_TFR; if (s->errintstsen & SDHC_EISEN_ADMAERR) { - ERRPRINT("Set ADMA error flag\n"); + trace_sdhci_error("Set ADMA error flag"); s->errintsts |=3D SDHC_EIS_ADMAERR; s->norintsts |=3D SDHC_NIS_ERR; } @@ -810,7 +782,7 @@ static void sdhci_data_transfer(void *opaque) break; case SDHC_CTRL_ADMA1_32: if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { - ERRPRINT("ADMA1 not supported\n"); + trace_sdhci_error("ADMA1 not supported"); break; } =20 @@ -818,7 +790,7 @@ static void sdhci_data_transfer(void *opaque) break; case SDHC_CTRL_ADMA2_32: if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { - ERRPRINT("ADMA2 not supported\n"); + trace_sdhci_error("ADMA2 not supported"); break; } =20 @@ -827,14 +799,14 @@ static void sdhci_data_transfer(void *opaque) case SDHC_CTRL_ADMA2_64: if (!(s->capareg & SDHC_CAN_DO_ADMA2) || !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { - ERRPRINT("64 bit ADMA not supported\n"); + trace_sdhci_error("64 bit ADMA not supported"); break; } =20 sdhci_do_adma(s); break; default: - ERRPRINT("Unsupported DMA type\n"); + trace_sdhci_error("Unsupported DMA type"); break; } } else { @@ -869,8 +841,8 @@ static inline bool sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) { if ((s->data_count & 0x3) !=3D byte_num) { - ERRPRINT("Non-sequential access to Buffer Data Port register" - "is prohibited\n"); + trace_sdhci_error("Non-sequential access to Buffer Data Port regis= ter" + "is prohibited\n"); return false; } return true; @@ -900,8 +872,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,= unsigned size) case SDHC_BDATA: if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { ret =3D sdhci_read_dataport(s, size); - DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)o= ffset, - ret, ret); + trace_sdhci_access("read", size, offset, "->", ret, ret); return ret; } break; @@ -953,7 +924,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,= unsigned size) =20 ret >>=3D (offset & 0x3) * 8; ret &=3D (1ULL << (size * 8)) - 1; - DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, r= et, ret); + trace_sdhci_access("read", size, offset, "->", ret, ret); return ret; } =20 @@ -1157,8 +1128,8 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) "not implemented\n", size, offset, value >> shift); break; } - DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", - size, (int)offset, value >> shift, value >> shift); + trace_sdhci_access("write", size, offset, "<-", + value >> shift, value >> shift); } =20 static const MemoryRegionOps sdhci_mmio_ops =3D { diff --git a/hw/sd/trace-events b/hw/sd/trace-events index 1fc0bcf44b..e4e26c6d73 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -1,5 +1,19 @@ # See docs/devel/tracing.txt for syntax documentation. =20 +# hw/sd/sdhci.c +sdhci_set_inserted(const char *level) "card state changed: %s" +sdhci_send_command(uint8_t cmd, uint32_t arg) "sending CMD%02u ARG[0x%08x]" +sdhci_error(const char *msg) "%s" +sdhci_response4(uint32_t r0) "Response: RSPREG[31..0]=3D0x%08x" +sdhci_response16(uint32_t r3, uint32_t r2, uint32_t r1, uint32_t r0) "Resp= onse received: RSPREG[127..96]=3D0x%08x, RSPREG[95..64]=3D0x%08x, RSPREG[63= ..32]=3D0x%08x, RSPREG[31..0]=3D0x%08x" +sdhci_end_transfer(uint8_t cmd, uint32_t arg) "Automatically issue CMD%02u= 0x%08x" +sdhci_adma(const char *desc, uint32_t sysad) "ADMA %s: admasysaddr=3D0x%" = PRIx32 +sdhci_adma_loop(uint64_t addr, uint16_t length, uint8_t attr) "ADMA loop: = addr=3D0x%08" PRIx64 ", len=3D%d, attr=3D0x%x" +sdhci_adma_transfer_completed(void) "ADMA transfer completed" +sdhci_access(const char *access, unsigned int size, uint64_t offset, const= char *dir, uint64_t val, uint64_t val2) "%s %ub: addr[0x%04" PRIx64 "] %s = %" PRIu64 "(0x%" PRIx64 ")" +sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been r= ead from input buffer" +sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u byt= es of data" + # hw/sd/milkymist-memcard.c milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x = value 0x%08x" milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x= value 0x%08x" --=20 2.15.1