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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.31.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:31:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t1rtS4W0E0o4pDhQjDsb/TkaBBm0GmPmdNHWbu+8Iw8=; b=iCUz624Nuvy70IBP+jRpMZk2nL/SSU5LCaXEsYCD+OZnOILrbhe7WNzm5kT69tym+Y kvgxQXz3fO29otzSZHtoiX1R7d9yZ+PUH9aD5fogh9bs4JLOQs6RGLJi8nbamcwl7pac kztFO4HlCSWnkJuYCdY2PCKxi1Z1+qvWQv6G8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t1rtS4W0E0o4pDhQjDsb/TkaBBm0GmPmdNHWbu+8Iw8=; b=Ca/lbCFjldgIVG1hd/hkZ7CnKFiY0DsAxXVBA7Ty9HWyeEB1d1kewUbamvc52cXZwE 680fytl27evcYIlQ2jtAEUMA5QgRSWPpMHUnLceFFeVnRSjEDYHoCW2Q7mBYRIpICc6I IUCzclD6S/V1hwm3P+206qx6AhyrkIrdTGvCibolswQBpxv+sbRHqRq2JXiZblfAXSsz sas8AN9aJUrdiBL7MT2dxELsuDCdu7ky4OrAE6wlCbX7JtoDkeRIKaNZ9tKlj++9c+YJ KZIQZTzIkXuATVVBiJAKqM+87GuvHZj3+sC8gKf4Bmo6f0LAB2SbQR14ygQOpnwJs24F zp0g== X-Gm-Message-State: AKGB3mKSiu4Foxq0RwSupZIxvgdGCYpwlpe6EPantlWjxHeHJ74Spk3b ZKwXMf9m/3KzPrhAnREK3jVVI2aTuqM= X-Google-Smtp-Source: ACJfBoszhwkQZtoaMVwuHLFYyO6nL1yc67Ha0gcvgRZJq4xfVEzj1K/AUTBvRXAG1wAmwTwscWC1Mg== X-Received: by 10.98.155.129 with SMTP id e1mr34638317pfk.119.1514529119195; Thu, 28 Dec 2017 22:31:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:15 -0800 Message-Id: <20171229063145.29167-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 08/38] target/hppa: Add space registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/helper.c | 14 ++++++---- target/hppa/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++= ---- 3 files changed, 77 insertions(+), 11 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 805c93db9c..24c728c0d2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -140,6 +140,7 @@ typedef int64_t target_sreg; struct CPUHPPAState { target_ureg gr[32]; uint64_t fr[32]; + uint64_t sr[8]; /* stored shifted into place for gva */ =20 target_ureg sar; target_ureg cr26; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b6521f61fc..608b30fe65 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -168,12 +168,16 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, psw, psw_cb, psw_c); =20 for (i =3D 0; i < 32; i++) { - cpu_fprintf(f, "GR%02d " TREG_FMT_lx " ", i, env->gr[i]); - if ((i % 4) =3D=3D 3) { - cpu_fprintf(f, "\n"); - } + cpu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + (i & 4) =3D=3D 3 ? '\n' : ' '); + } +#ifndef CONFIG_USER_ONLY + for (i =3D 0; i < 8; i++) { + cpu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), + (i & 4) =3D=3D 3 ? '\n' : ' '); } - cpu_fprintf(f, "\n"); +#endif + cpu_fprintf(f, "\n"); =20 /* ??? FR */ } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6f165fdd3d..08829f5de9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -317,6 +317,7 @@ typedef struct DisasInsn { =20 /* global register indexes */ static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_sr[4]; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_reg cpu_sar; @@ -355,6 +356,10 @@ void hppa_translate_init(void) "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; + /* SR[4-7] are not global registers so that we can index them. */ + static const char sr_names[4][4] =3D { + "sr0", "sr1", "sr2", "sr3" + }; =20 int i; =20 @@ -364,6 +369,11 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, gr[i]), gr_names[i]); } + for (i =3D 0; i < 4; i++) { + cpu_sr[i] =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[i]), + sr_names[i]); + } =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; @@ -568,6 +578,19 @@ static void save_frd(unsigned rt, TCGv_i64 val) tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); } =20 +static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) +{ +#ifdef CONFIG_USER_ONLY + tcg_gen_movi_i64(dest, 0); +#else + if (reg < 4) { + tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else { + tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); + } +#endif +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -782,6 +805,13 @@ static unsigned assemble_rc64(uint32_t insn) return r2 * 32 + r1 * 4 + r0; } =20 +static unsigned assemble_sr3(uint32_t insn) +{ + unsigned s2 =3D extract32(insn, 13, 1); + unsigned s0 =3D extract32(insn, 14, 2); + return s2 * 4 + s0; +} + static target_sreg assemble_12(uint32_t insn) { target_ureg x =3D -(target_ureg)(insn & 1); @@ -1884,11 +1914,17 @@ static DisasJumpType trans_mfsp(DisasContext *ctx, = uint32_t insn, const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tmp =3D dest_gpr(ctx, rt); + unsigned rs =3D assemble_sr3(insn); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_reg t1 =3D tcg_temp_new(); =20 - /* ??? We don't implement space registers. */ - tcg_gen_movi_reg(tmp, 0); - save_gpr(ctx, rt, tmp); + load_spr(ctx, t0, rs); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_reg(t1, t0); + + save_gpr(ctx, rt, t1); + tcg_temp_free(t1); + tcg_temp_free_i64(t0); =20 cond_free(&ctx->null_cond); return DISAS_NEXT; @@ -1934,6 +1970,32 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, = uint32_t insn, return DISAS_NEXT; } =20 +static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr =3D extract32(insn, 16, 5); + unsigned rs =3D assemble_sr3(insn); + TCGv_i64 t64; + + if (rs >=3D 5) { + CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); + } + nullify_over(ctx); + + t64 =3D tcg_temp_new_i64(); + tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); + tcg_gen_shli_i64(t64, t64, 32); + + if (rs >=3D 4) { + tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + } else { + tcg_gen_mov_i64(cpu_sr[rs], t64); + } + tcg_temp_free_i64(t64); + + return nullify_end(ctx, DISAS_NEXT); +} + static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -2059,8 +2121,7 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, ui= nt32_t insn, =20 static const DisasInsn table_system[] =3D { { 0x00000000u, 0xfc001fe0u, trans_break }, - /* We don't implement space register, so MTSP is a nop. */ - { 0x00001820u, 0xffe01fffu, trans_nop }, + { 0x00001820u, 0xffe01fffu, trans_mtsp }, { 0x00001840u, 0xfc00ffffu, trans_mtctl }, { 0x016018c0u, 0xffe0ffffu, trans_mtsarcm }, { 0x000014a0u, 0xffffffe0u, trans_mfia }, --=20 2.14.3