From nobody Fri Dec 19 06:29:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1514529266519602.6717715954641; Thu, 28 Dec 2017 22:34:26 -0800 (PST) Received: from localhost ([::1]:56935 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoFN-0004JI-DL for importer@patchew.org; Fri, 29 Dec 2017 01:34:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoD3-0002rm-7m for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eUoD0-0004Xk-0G for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:01 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:43806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eUoCz-0004Xa-OH for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:31:57 -0500 Received: by mail-pg0-x244.google.com with SMTP id f18so4054369pga.10 for ; Thu, 28 Dec 2017 22:31:57 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.31.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:31:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fswcJ3IGO+WM4z0dDtz8pwBtopH2fX4haLdkOFHPWKQ=; b=KsBmftZ9kF+kHQXgkPghWV70hCaRPrq3d2bCpd/zuGeqn21H2aCzNej7noJqtwVz7F YQ+6euT/M46UYkSnF4No/ANZCQ+JHGjCl6TJzp4+xCD6lINDp2SQaRqH/KqHOLvh2I9Q MQSL4GPrEfbMjQ7RKcFVTg6Aa6iN65R5mt/68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fswcJ3IGO+WM4z0dDtz8pwBtopH2fX4haLdkOFHPWKQ=; b=O+At7HLN+KQWNUyqKgZcnxWG3M6IaTThoczQkG+tIlLL4yT+qkHr7HFr32/lTYz84G EQp4Q2cI8NcvJy1Gn/Sx7vAU6+VPet+CauRvZaQaBnF84yl5wn7SUo0TrYHb4iR98lz/ ij3rcJKeJumI7YH6EevNAyI4b4Q+DrwDTf1Mq2U2gwFiqdhEapTGBMu2jdva0XEx+6nj xRevt0P8poExiZz79lydJBs8rfojbd3SdgpyMvG/IxnphFXShksliwxJx3170Hn87AFu npToF5ShiI/9IyTdfXGv8/+SA/qZpYv9INZ7bB4Jkqk46z8K0AAd3mdAzMyEbvKiTjFR mT8A== X-Gm-Message-State: AKGB3mLBVLzT4BVmKi62jupiD+ndKtO48l+Zq7GVIWvxSGz441CLj4iy 5jwfO00+yTQtVLT5e3B4DbYxcnao4fo= X-Google-Smtp-Source: ACJfBoswjLrYKvZT8MxJs4/pvPbrYsdEfBGilXjhl4Uu4j7s1skKa7NoW01ityQYUSNKHDUbkNB1mg== X-Received: by 10.99.110.131 with SMTP id j125mr2467027pgc.241.1514529116288; Thu, 28 Dec 2017 22:31:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:13 -0800 Message-Id: <20171229063145.29167-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 06/38] target/hppa: Implement mmu_idx from IA privilege level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Most aspects of privilege are not yet handled. But this gives us the start from which to begin checking. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 19 +++++++++++++---- target/hppa/cpu.c | 2 +- target/hppa/translate.c | 54 +++++++++++++++++++++++++++++++++------------= ---- 3 files changed, 53 insertions(+), 22 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1524ef91b6..805c93db9c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -36,8 +36,10 @@ #define TARGET_PAGE_BITS 12 =20 #define ALIGNED_ONLY -#define NB_MMU_MODES 1 -#define MMU_USER_IDX 0 +#define NB_MMU_MODES 5 +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_PHYS_IDX 4 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 /* Hardware exceptions, interupts, faults, and traps. */ @@ -195,7 +197,14 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *= env) =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { - return 0; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return env->iaoq_f & 3; + } + return MMU_PHYS_IDX; /* mmu disabled */ +#endif } =20 void hppa_translate_init(void); @@ -210,7 +219,9 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, target_ulong *pc, { *pc =3D env->iaoq_f; *cs_base =3D env->iaoq_b; - *pflags =3D env->psw_n; + /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ + *pflags =3D (env->psw & (PSW_W | PSW_C | PSW_D)) + | env->psw_n * PSW_N; } =20 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f6d92de972..9962ab71ee 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -39,7 +39,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) =20 cpu->env.iaoq_f =3D tb->pc; cpu->env.iaoq_b =3D tb->cs_base; - cpu->env.psw_n =3D tb->flags & 1; + cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b3996cfcdc..7afd91b69d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -278,6 +278,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + int mmu_idx; + int privilege; bool psw_n_nonzero; } DisasContext; =20 @@ -1288,10 +1290,10 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 = dest, unsigned rb, } =20 if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i32(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i32(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1318,10 +1320,10 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 = dest, unsigned rb, } =20 if (modify =3D=3D 0) { - tcg_gen_qemu_ld_i64(dest, addr, MMU_USER_IDX, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); } else { tcg_gen_qemu_ld_i64(dest, (modify < 0 ? addr : base), - MMU_USER_IDX, mop); + ctx->mmu_idx, mop); save_gpr(ctx, rb, addr); } tcg_temp_free(addr); @@ -1347,7 +1349,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } =20 - tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); + tcg_gen_qemu_st_i32(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); =20 if (modify !=3D 0) { save_gpr(ctx, rb, addr); @@ -1375,7 +1377,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, tcg_gen_addi_reg(addr, base, disp); } =20 - tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), MMU_USER_IDX, = mop); + tcg_gen_qemu_st_i64(src, (modify <=3D 0 ? addr : base), ctx->mmu_idx, = mop); =20 if (modify !=3D 0) { save_gpr(ctx, rb, addr); @@ -2486,7 +2488,7 @@ static DisasJumpType trans_ldcw(DisasContext *ctx, ui= nt32_t insn, =20 zero =3D tcg_const_reg(0); tcg_gen_atomic_xchg_reg(dest, (modify <=3D 0 ? addr : base), - zero, MMU_USER_IDX, mop); + zero, ctx->mmu_idx, mop); if (modify) { save_gpr(ctx, rb, addr); } @@ -3960,30 +3962,48 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs, int max_insns) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - TranslationBlock *tb =3D ctx->base.tb; int bound; =20 ctx->cs =3D cs; - ctx->iaoq_f =3D tb->pc; - ctx->iaoq_b =3D tb->cs_base; + +#ifdef CONFIG_USER_ONLY + ctx->privilege =3D MMU_USER_IDX; + ctx->mmu_idx =3D MMU_USER_IDX; +#else + ctx->privilege =3D ctx->base.pc_first & 3; + ctx->mmu_idx =3D (ctx->base.tb->flags & PSW_D + ? ctx->privilege : MMU_PHYS_IDX); +#endif + ctx->iaoq_f =3D ctx->base.pc_first; + ctx->iaoq_b =3D ctx->base.tb->cs_base; + ctx->base.pc_first &=3D -4; + ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 + /* Bound the number of instructions by those left on the page. */ + bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + bound =3D MIN(max_insns, bound); + + /* If the instruction queue includes a priority change, split the TB. = */ + if ((ctx->iaoq_f ^ ctx->iaoq_b) & 3) { + bound =3D 1; + } + ctx->ntemps =3D 0; memset(ctx->temps, 0, sizeof(ctx->temps)); =20 - bound =3D -(tb->pc | TARGET_PAGE_MASK) / 4; - return MIN(max_insns, bound); + return bound; } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. = */ + /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. = */ ctx->null_cond =3D cond_make_f(); ctx->psw_n_nonzero =3D false; - if (ctx->base.tb->flags & 1) { + if (ctx->base.tb->flags & PSW_N) { ctx->null_cond.c =3D TCG_COND_ALWAYS; ctx->psw_n_nonzero =3D true; } @@ -4003,7 +4023,7 @@ static bool hppa_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cs, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next =3D ctx->iaoq_f + 4; + ctx->base.pc_next =3D (ctx->iaoq_f & -4) + 4; return true; } =20 @@ -4024,7 +4044,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ - uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f); + uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f & -4); =20 /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ @@ -4110,7 +4130,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) =20 /* We don't actually use this during normal translation, but we should interact with the generic main loop. */ - ctx->base.pc_next =3D ctx->base.tb->pc + 4 * ctx->base.num_insns; + ctx->base.pc_next =3D ctx->base.pc_first + 4 * ctx->base.num_insns; } =20 static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) --=20 2.14.3