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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.32.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:32:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gh1U/7BNcHgKD9YaPWLb3n0G80IXT+Fjoxmdsd+u74Y=; b=Bgh79bOQxF4F1Gt+bWwtkCY+NkSzb2BwLZGUBJN4AcM2yyssIPbsSpGkjPqdLcNlUM T4+39Bg9Z+f1rPKuK5tpAVZ54X1vsl/usgigJNrDitm5xuyhIZ+KNIOkENhFGyTPswDh RUvTRgv8mo0mEFic/XiuOgDOW3AWzx9Jbyf3g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gh1U/7BNcHgKD9YaPWLb3n0G80IXT+Fjoxmdsd+u74Y=; b=bw6hyhANgDeGBLCN4Ba53LoawrN79IPLbd2NJtHJ/ABoqS7tAY+l4LtJMapkTenTw1 n3XDk40IPlbBffH/xhQeO77rJ2jPHP4itGiJX+iyG5zTFiPpMUpV2sxml70g50sUn1lb 4oKQvobNyvqDMKpSTsXbNASgZ9+QYVF2/4d2K2gTSlZD6js9MU00umwbOoelqNYrvcUm 9CeAScwoUQ9IXlnM5t4aBrI/1G7ZJskXkYwljQPyNHxm7fWheQd2oDkynZephiLCw3oS fvG/KlAJ07UabDj52n4zSWCqubrXTrZkAgpTQgakn6frHHR8BpP43NV0hnQr5FsuWjRy PYOA== X-Gm-Message-State: AKGB3mK1I+q9qPQJmPBAms30DR8j5enluZlKyslws4WTOGe9LxMO7U+Q +uvaIu+5jW128B8IQaM+HoPjlMDJKp4= X-Google-Smtp-Source: ACJfBou090Uo2hcKwQOkAdQvmwfz/BdyEdTa0rAyjYtweQ1/HPwE6TOkDtvbS23JStnQta5yIE/NhQ== X-Received: by 10.98.58.208 with SMTP id v77mr34356179pfj.150.1514529151500; Thu, 28 Dec 2017 22:32:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:40 -0800 Message-Id: <20171229063145.29167-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 33/38] target/hppa: Implement B,GATE insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 8 ++++++++ target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 57 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 648b78986e..0f8db1ec75 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -352,6 +352,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_= t ra); =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9d93894019..e2f94faab5 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -123,6 +123,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, break; default: /* execute: promote to privilege level type & 3 */ prot =3D x_prot; + break; } =20 /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. = */ @@ -318,4 +319,11 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulon= g addr) } return phys; } + +/* Return the ar_type of the TLB at VADDR, or -1. */ +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) +{ + hppa_tlb_entry *ent =3D hppa_find_tlb(env, vaddr); + return ent ? ent->ar_type : -1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 23ec43eff8..4430a4bfdb 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3769,6 +3769,53 @@ static DisasJumpType trans_bl(DisasContext *ctx, uin= t32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } =20 +static DisasJumpType trans_b_gate(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned n =3D extract32(insn, 1, 1); + unsigned link =3D extract32(insn, 21, 5); + target_sreg disp =3D assemble_17(insn); + target_ureg dest =3D iaoq_dest(ctx, disp); + + /* Make sure the caller hasn't done something weird with the queue. + * ??? This is not quite the same as the PSW[B] bit, which would be + * expensive to track. Real hardware will trap for + * b gateway + * b gateway+4 (in delay slot of first branch) + * However, checking for a non-sequential instruction queue *will* + * diagnose the security hole + * b gateway + * b evil + * in which instructions at evil would run with increased privs. + */ + if (ctx->iaoq_b =3D=3D -1 || ctx->iaoq_b !=3D ctx->iaoq_f + 4) { + return gen_illegal(ctx); + } + +#ifndef CONFIG_USER_ONLY + if (ctx->tb_flags & PSW_C) { + CPUHPPAState *env =3D ctx->cs->env_ptr; + int type =3D hppa_artype_for_page(env, ctx->base.pc_next); + /* If we could not find a TLB entry, then we need to generate an + ITLB miss exception so the kernel will provide it. + The resulting TLB fill operation will invalidate this TB and + we will re-translate, at which point we *will* be able to find + the TLB entry and determine if this is in fact a gateway page. = */ + if (type < 0) { + return gen_excp(ctx, EXCP_ITLB_MISS); + } + /* No change for non-gateway pages or for priv decrease. */ + if (type >=3D 4 && type - 4 < ctx->privilege) { + dest =3D deposit32(dest, 0, 2, type - 4); + } + } else { + dest &=3D -4; /* priv =3D 0 */ + } +#endif + + return do_dbranch(ctx, dest, link, n); +} + static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -3847,6 +3894,7 @@ static const DisasInsn table_branch[] =3D { { 0xe8004000u, 0xfc00fffdu, trans_blr }, { 0xe800c000u, 0xfc00fffdu, trans_bv }, { 0xe800d000u, 0xfc00dffcu, trans_bve }, + { 0xe8002000u, 0xfc00e000u, trans_b_gate }, }; =20 static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, --=20 2.14.3