From nobody Fri Dec 19 06:30:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1514529834095386.86839409343327; Thu, 28 Dec 2017 22:43:54 -0800 (PST) Received: from localhost ([::1]:56991 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoOW-0004C6-Rw for importer@patchew.org; Fri, 29 Dec 2017 01:43:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoDC-00030J-W4 for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eUoDB-0004fq-Nj for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:11 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:41788) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eUoDB-0004fY-Hp for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:09 -0500 Received: by mail-pf0-x242.google.com with SMTP id j28so21823768pfk.8 for ; Thu, 28 Dec 2017 22:32:09 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.32.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:32:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rjZPUs93e0buGAYTYvnlaGPueYguXZn49mR22zU910I=; b=A0V3HqUQptajiM7q14qq0nIyl+7CxKm7/09o2ipF/8TVnU3m677FSIfrXikiIyM+ev W9vynhdUyBGln5B7QwjSxkPVaBoQGo1uJpP9B5pCNx7AXEnGHfJNBAoItZicPmedjuBW Dm7LC1sAobzvlMxJ894K+kDmOIofoKaTpzNBo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rjZPUs93e0buGAYTYvnlaGPueYguXZn49mR22zU910I=; b=GtQIh2sBfvTN7m4BYNALhopR+jxk7Skivfa4KI8riH6JflJiDfKBX9TkOLrWR+S8uF ZeyYLYa6QRsBtwstZsKxdXYk9k5mzJK2qDvqyRiMd/yyt8cJUYQKo9S6P3YIMqcBi7Vj 4SsQzivSa/2xmPJH0e5Bw542lrAE9cNLPQdKa7X5jKRBFFNn0rAAnmpUDXmQcahBiX5z fvO3dLWugmchpAiWBCdoL5het06j6NR0s9yIDFchlfqwSDfgH7vvYk9clUWGO83FuDrR YlqnLe+3rhNmPdCa108Bz35/Yk6XpsabuKcJaq5/hX2n3bhSfPjP1icN5j4LZQJdue5Q 5jXA== X-Gm-Message-State: AKGB3mLAymOqPDvMpYiTz3uVFoL3wlRi6Js7UvezB5kTKjnciDp5+1k1 9+OzzCceYJHJ61TC6rk3I+qXADlxGsw= X-Google-Smtp-Source: ACJfBosPs2SPmvD+0ix/BOBA0SBJ10vhM3KVg6GO5j5wEzaG0x59zDYo4fIIVAwN6KkmHmKLJ38OaQ== X-Received: by 10.101.102.19 with SMTP id w19mr2915168pgv.102.1514529128230; Thu, 28 Dec 2017 22:32:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:22 -0800 Message-Id: <20171229063145.29167-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 15/38] target/hppa: Do not set cs_base to iaoq_b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will need to use cs_base for iasq_f. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 13 +++++++++++-- target/hppa/cpu.c | 4 +++- target/hppa/translate.c | 22 ++++++++++++---------- 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 94f9c8ca2b..babad0d2c1 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -240,15 +240,24 @@ void hppa_translate_init(void); =20 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 +/* Since PSW_V will never need to be in tb->flags, reuse it. + * TB_FLAG_NONSEQ indicates that the two instructions in the insn queue + * are non-sequential. + */ +#define TB_FLAG_NONSEQ PSW_V + static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, target_ulong *cs_base, uint32_t *pflags) { + bool nonseq =3D env->iaoq_b !=3D env->iaoq_f + 4; + *pc =3D env->iaoq_f; - *cs_base =3D env->iaoq_b; + *cs_base =3D 0; /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ *pflags =3D (env->psw & (PSW_W | PSW_C | PSW_D)) - | env->psw_n * PSW_N; + | env->psw_n * PSW_N + | nonseq * TB_FLAG_NONSEQ; } =20 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6b2d22118d..715233c59a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -38,7 +38,9 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) HPPACPU *cpu =3D HPPA_CPU(cs); =20 cpu->env.iaoq_f =3D tb->pc; - cpu->env.iaoq_b =3D tb->cs_base; + if (!(tb->flags & TB_FLAG_NONSEQ)) { + cpu->env.iaoq_b =3D tb->pc + 4; + } cpu->env.psw_n =3D (tb->flags & PSW_N) !=3D 0; } =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e0d626dfe1..4d5974c94d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -770,9 +770,9 @@ static void gen_goto_tb(DisasContext *ctx, int which, target_ureg f, target_ureg b) { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { + tcg_gen_movi_reg(cpu_iaoq_b, b); tcg_gen_goto_tb(which); tcg_gen_movi_reg(cpu_iaoq_f, f); - tcg_gen_movi_reg(cpu_iaoq_b, b); tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -1792,11 +1792,17 @@ static DisasJumpType do_ibranch(DisasContext *ctx, = TCGv_reg dest, } next =3D get_temp(ctx); tcg_gen_mov_reg(next, dest); - ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D next; if (is_n) { + if (use_nullify_skip(ctx)) { + tcg_gen_mov_reg(cpu_iaoq_f, next); + tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + nullify_set(ctx, 0); + return DISAS_IAQ_N_UPDATED; + } ctx->null_cond.c =3D TCG_COND_ALWAYS; } + ctx->iaoq_n =3D -1; + ctx->iaoq_n_var =3D next; } else if (is_n && use_nullify_skip(ctx)) { /* The (conditional) branch, B, nullifies the next insn, N, and we're allowed to skip execution N (no single-step or @@ -4222,7 +4228,8 @@ static int hppa_tr_init_disas_context(DisasContextBas= e *dcbase, ? ctx->privilege : MMU_PHYS_IDX); #endif ctx->iaoq_f =3D ctx->base.pc_first; - ctx->iaoq_b =3D ctx->base.tb->cs_base; + ctx->iaoq_b =3D (ctx->base.tb->flags & TB_FLAG_NONSEQ + ? -1 : ctx->iaoq_f + 4); ctx->base.pc_first &=3D -4; =20 ctx->iaoq_n =3D -1; @@ -4232,11 +4239,6 @@ static int hppa_tr_init_disas_context(DisasContextBa= se *dcbase, bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; bound =3D MIN(max_insns, bound); =20 - /* If the instruction queue includes a priority change, split the TB. = */ - if ((ctx->iaoq_f ^ ctx->iaoq_b) & 3) { - bound =3D 1; - } - ctx->ntempr =3D 0; ctx->ntempl =3D 0; memset(ctx->tempr, 0, sizeof(ctx->tempr)); @@ -4440,7 +4442,7 @@ void restore_state_to_opc(CPUHPPAState *env, Translat= ionBlock *tb, target_ulong *data) { env->iaoq_f =3D data[0]; - if (data[1] !=3D -1) { + if (data[1] !=3D (target_ureg)-1) { env->iaoq_b =3D data[1]; } /* Since we were executing the instruction at IAOQ_F, and took some --=20 2.14.3