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[97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.32.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:32:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xpsShIzoBQuYIf0MxxzJfSsKBhIrJVvHBj/ufoKOyMc=; b=eI/DONKm2Ftx0vX/PCNQNVJDCm2Ye62iL6fu2YaPBtOiIISYDMCNAZELL/gbW3csaz /wtijWr6GDZAI6cbCp0RY+bpiBk7EX7QMTV6TNZ06Y/iiesGfSfsM+su25Xrs4LNILbN QSX5L7nOz535dQB8ZtbnLaayen3psblf3zzkw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xpsShIzoBQuYIf0MxxzJfSsKBhIrJVvHBj/ufoKOyMc=; b=JSgjoszCUMz5dJvUZSnvlv6TYeoDb5UcSjL0R2pj+I+6MXBXxJ+7C0xrWchfb0hVQB +Js4ND9/usGg2Cl4N4VCFLD11tmKF/PL0Du4FFc0GXsgxUvMu/v7BtmkCHU7neR9m4uS AF7Fv6WsV8JEKqje43WV/Nj7/SRkoHT5Xl66xeqSye7GGa5t6FJg9/vz8xlSNwc2/Q7G 4dULYA5dBwzy76FBw8QJ4CcvKhaJAz3UqamLIXyPto4X3vHMiTzqtv0SCAzx9b9xKSZA ZkXC2PD1LiNO3dbTd2beNK+5gROgthny0uxSN0reuwrhGrhFGTFQBqxQSldyMT0qr4go 61Pw== X-Gm-Message-State: AKGB3mIvnSxQi0Xiuh63BvB1JNhcNX/nX4Sm9CQrsM4RLEU9OjUXuTkz vdIYblqwEcuRBxGWrG8lmkbQth39vxE= X-Google-Smtp-Source: ACJfBotVEKF9PlJiT05axbtxzSb/0mmiXm+kqJk7ftU+E3jWTCdlnvDcKptDZqbNJdv3C9kIdjFzFQ== X-Received: by 10.99.120.73 with SMTP id t70mr29299430pgc.402.1514529124194; Thu, 28 Dec 2017 22:32:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:19 -0800 Message-Id: <20171229063145.29167-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 12/38] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 2 + target/hppa/helper.c | 63 ----------------- target/hppa/int_helper.c | 176 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/hppa/translate.c | 16 ++++- target/hppa/Makefile.objs | 1 + 5 files changed, 192 insertions(+), 66 deletions(-) create mode 100644 target/hppa/int_helper.c diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 9962ab71ee..ca619578dd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,8 +106,10 @@ static void hppa_cpu_initfn(Object *obj) CPUHPPAState *env =3D &cpu->env; =20 cs->env_ptr =3D env; + cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); set_snan_bit_is_one(true, &env->fp_status); + cpu_hppa_put_psw(env, PSW_W); } =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 608b30fe65..cab50c6ddd 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -67,69 +67,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_cb =3D cb; } =20 -void hppa_cpu_do_interrupt(CPUState *cs) -{ - HPPACPU *cpu =3D HPPA_CPU(cs); - CPUHPPAState *env =3D &cpu->env; - int i =3D cs->exception_index; - - if (qemu_loglevel_mask(CPU_LOG_INT)) { - static const char * const names[] =3D { - [EXCP_HPMC] =3D "high priority machine check", - [EXCP_POWER_FAIL] =3D "power fail interrupt", - [EXCP_RC] =3D "recovery counter trap", - [EXCP_EXT_INTERRUPT] =3D "external interrupt", - [EXCP_LPMC] =3D "low priority machine check", - [EXCP_ITLB_MISS] =3D "instruction tlb miss fault", - [EXCP_IMP] =3D "instruction memory protection trap", - [EXCP_ILL] =3D "illegal instruction trap", - [EXCP_BREAK] =3D "break instruction trap", - [EXCP_PRIV_OPR] =3D "privileged operation trap", - [EXCP_PRIV_REG] =3D "privileged register trap", - [EXCP_OVERFLOW] =3D "overflow trap", - [EXCP_COND] =3D "conditional trap", - [EXCP_ASSIST] =3D "assist exception trap", - [EXCP_DTLB_MISS] =3D "data tlb miss fault", - [EXCP_NA_ITLB_MISS] =3D "non-access instruction tlb miss", - [EXCP_NA_DTLB_MISS] =3D "non-access data tlb miss", - [EXCP_DMP] =3D "data memory protection trap", - [EXCP_DMB] =3D "data memory break trap", - [EXCP_TLB_DIRTY] =3D "tlb dirty bit trap", - [EXCP_PAGE_REF] =3D "page reference trap", - [EXCP_ASSIST_EMU] =3D "assist emulation trap", - [EXCP_HPT] =3D "high-privilege transfer trap", - [EXCP_LPT] =3D "low-privilege transfer trap", - [EXCP_TB] =3D "taken branch trap", - [EXCP_DMAR] =3D "data memory access rights trap", - [EXCP_DMPI] =3D "data memory protection id trap", - [EXCP_UNALIGN] =3D "unaligned data reference trap", - [EXCP_PER_INTERRUPT] =3D "performance monitor interrupt", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_SYSCALL_LWS] =3D "syscall-lws", - }; - static int count; - const char *name =3D NULL; - - if (i >=3D 0 && i < ARRAY_SIZE(names)) { - name =3D names[i]; - } - if (name) { - qemu_log("INT %6d: %s ia_f=3D" TARGET_FMT_lx "\n", - ++count, name, env->iaoq_f); - } else { - qemu_log("INT %6d: unknown %d ia_f=3D" TARGET_FMT_lx "\n", - ++count, i, env->iaoq_f); - } - } - cs->exception_index =3D -1; -} - -bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - abort(); - return false; -} - void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c new file mode 100644 index 0000000000..34413c30e1 --- /dev/null +++ b/target/hppa/int_helper.c @@ -0,0 +1,176 @@ +/* + * HPPA interrupt helper routines + * + * Copyright (c) 2017 Richard Henderson + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qom/cpu.h" + + +void hppa_cpu_do_interrupt(CPUState *cs) +{ + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + int i =3D cs->exception_index; + target_ureg iaoq_f =3D env->iaoq_f; + target_ureg iaoq_b =3D env->iaoq_b; + +#ifndef CONFIG_USER_ONLY + target_ureg old_psw; + + /* As documented in pa2.0 -- interruption handling. */ + /* step 1 */ + env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); + + /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ + cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + + /* step 3 */ + env->cr[CR_IIAOQ] =3D iaoq_f; + env->cr_back[1] =3D iaoq_b; + + /* step 5 */ + /* ISR and IOR will be set elsewhere. */ + switch (i) { + case EXCP_ILL: + case EXCP_BREAK: + case EXCP_PRIV_REG: + case EXCP_PRIV_OPR: + /* IIR set via translate.c. */ + break; + + case EXCP_OVERFLOW: + case EXCP_COND: + case EXCP_ASSIST: + case EXCP_DTLB_MISS: + case EXCP_NA_ITLB_MISS: + case EXCP_NA_DTLB_MISS: + case EXCP_DMAR: + case EXCP_DMPI: + case EXCP_UNALIGN: + case EXCP_DMP: + case EXCP_DMB: + case EXCP_TLB_DIRTY: + case EXCP_PAGE_REF: + case EXCP_ASSIST_EMU: + { + /* Avoid reading directly from the virtual address, lest we + raise another exception from some sort of TLB issue. */ + vaddr vaddr; + hwaddr paddr; + + paddr =3D vaddr =3D iaoq_f & -4; + env->cr[CR_IIR] =3D ldl_phys(cs->as, paddr); + } + break; + + default: + /* Other exceptions do not set IIR. */ + break; + } + + /* step 6 */ + if (old_psw & PSW_Q) { + env->shadow[0] =3D env->gr[1]; + env->shadow[1] =3D env->gr[8]; + env->shadow[2] =3D env->gr[9]; + env->shadow[3] =3D env->gr[16]; + env->shadow[4] =3D env->gr[17]; + env->shadow[5] =3D env->gr[24]; + env->shadow[6] =3D env->gr[25]; + } + + /* step 7 */ + env->iaoq_f =3D env->cr[CR_IVA] + 32 * i; + env->iaoq_b =3D env->iaoq_f + 4; +#endif + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + static const char * const names[] =3D { + [EXCP_HPMC] =3D "high priority machine check", + [EXCP_POWER_FAIL] =3D "power fail interrupt", + [EXCP_RC] =3D "recovery counter trap", + [EXCP_EXT_INTERRUPT] =3D "external interrupt", + [EXCP_LPMC] =3D "low priority machine check", + [EXCP_ITLB_MISS] =3D "instruction tlb miss fault", + [EXCP_IMP] =3D "instruction memory protection trap", + [EXCP_ILL] =3D "illegal instruction trap", + [EXCP_BREAK] =3D "break instruction trap", + [EXCP_PRIV_OPR] =3D "privileged operation trap", + [EXCP_PRIV_REG] =3D "privileged register trap", + [EXCP_OVERFLOW] =3D "overflow trap", + [EXCP_COND] =3D "conditional trap", + [EXCP_ASSIST] =3D "assist exception trap", + [EXCP_DTLB_MISS] =3D "data tlb miss fault", + [EXCP_NA_ITLB_MISS] =3D "non-access instruction tlb miss", + [EXCP_NA_DTLB_MISS] =3D "non-access data tlb miss", + [EXCP_DMP] =3D "data memory protection trap", + [EXCP_DMB] =3D "data memory break trap", + [EXCP_TLB_DIRTY] =3D "tlb dirty bit trap", + [EXCP_PAGE_REF] =3D "page reference trap", + [EXCP_ASSIST_EMU] =3D "assist emulation trap", + [EXCP_HPT] =3D "high-privilege transfer trap", + [EXCP_LPT] =3D "low-privilege transfer trap", + [EXCP_TB] =3D "taken branch trap", + [EXCP_DMAR] =3D "data memory access rights trap", + [EXCP_DMPI] =3D "data memory protection id trap", + [EXCP_UNALIGN] =3D "unaligned data reference trap", + [EXCP_PER_INTERRUPT] =3D "performance monitor interrupt", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_SYSCALL_LWS] =3D "syscall-lws", + }; + static int count; + const char *name =3D NULL; + char unknown[16]; + + if (i >=3D 0 && i < ARRAY_SIZE(names)) { + name =3D names[i]; + } + if (!name) { + snprintf(unknown, sizeof(unknown), "unknown %d", i); + name =3D unknown; + } + qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx + " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + ++count, name, + (target_ulong)iaoq_f, + (target_ulong)iaoq_b, + env->iaoq_f, + (target_ulong)env->cr[CR_IOR]); + } + cs->exception_index =3D -1; +} + +bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ +#ifndef CONFIG_USER_ONLY + HPPACPU *cpu =3D HPPA_CPU(cs); + CPUHPPAState *env =3D &cpu->env; + + /* If interrupts are requested and enabled, raise them. */ + if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + cs->exception_index =3D EXCP_EXT_INTERRUPT; + hppa_cpu_do_interrupt(cs); + return true; + } +#endif + return false; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8078d3cd46..e6a9adc3c7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -278,6 +278,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + uint32_t insn; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -714,17 +715,25 @@ static DisasJumpType gen_excp(DisasContext *ctx, int = exception) return DISAS_NORETURN; } =20 +static DisasJumpType gen_excp_iir(DisasContext *ctx, int exc) +{ + TCGv_reg tmp =3D tcg_const_reg(ctx->insn); + tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); + tcg_temp_free(tmp); + return gen_excp(ctx, exc); +} + static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_ILL)); } =20 #define CHECK_MOST_PRIVILEGED(EXCP) \ do { \ if (ctx->privilege !=3D 0) { \ nullify_over(ctx); \ - return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + return nullify_end(ctx, gen_excp_iir(ctx, EXCP)); \ } \ } while (0) =20 @@ -1884,7 +1893,7 @@ static DisasJumpType trans_break(DisasContext *ctx, u= int32_t insn, const DisasInsn *di) { nullify_over(ctx); - return nullify_end(ctx, gen_excp(ctx, EXCP_BREAK)); + return nullify_end(ctx, gen_excp_iir(ctx, EXCP_BREAK)); } =20 static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, @@ -4266,6 +4275,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ctx->null_cond.c =3D TCG_COND_NEVER; ret =3D DISAS_NEXT; } else { + ctx->insn =3D insn; ret =3D translate_one(ctx, insn); assert(ctx->null_lab =3D=3D NULL); } diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs index d89285307b..dcd60a6839 100644 --- a/target/hppa/Makefile.objs +++ b/target/hppa/Makefile.objs @@ -1 +1,2 @@ obj-y +=3D translate.o helper.o cpu.o op_helper.o gdbstub.o mem_helper.o +obj-y +=3D int_helper.o --=20 2.14.3