From nobody Wed Feb 11 01:08:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513844768052343.20838189147776; Thu, 21 Dec 2017 00:26:08 -0800 (PST) Received: from localhost ([::1]:38800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eRwB2-0007V6-EZ for importer@patchew.org; Thu, 21 Dec 2017 03:26:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eRw6L-0003iq-Ki for qemu-devel@nongnu.org; Thu, 21 Dec 2017 03:21:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eRw6F-0004TG-BD for qemu-devel@nongnu.org; Thu, 21 Dec 2017 03:21:13 -0500 Received: from chuckie.co.uk ([82.165.15.123]:43124 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eRw6E-0004R8-VC for qemu-devel@nongnu.org; Thu, 21 Dec 2017 03:21:07 -0500 Received: from [86.188.254.49] (helo=kentang.int.eigen.co) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eRw6N-0000vT-6k; Thu, 21 Dec 2017 08:21:16 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Thu, 21 Dec 2017 08:20:38 +0000 Message-Id: <20171221082045.14022-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171221082045.14022-1-mark.cave-ayland@ilande.co.uk> References: <20171221082045.14022-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.188.254.49 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 09/16] apb: move the two secondary PCI bridges objects into APBState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This enables us to remove these parameters from pci_apb_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/apb.c | 14 +++++--------- hw/sparc64/sun4u.c | 5 ++++- include/hw/pci-host/apb.h | 5 +++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index c0b97e41bf..823661a8a6 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -612,8 +612,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Erro= r **errp) } =20 APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - PCIBus **busA, PCIBus **busB) + hwaddr mem_base) { DeviceState *dev; SysBusDevice *s; @@ -621,7 +620,6 @@ APBState *pci_apb_init(hwaddr special_base, APBState *d; IOMMUState *is; PCIDevice *pci_dev; - PCIBridge *br; =20 /* Ultrasparc PBM main bus */ dev =3D qdev_create(NULL, TYPE_APB); @@ -659,18 +657,16 @@ APBState *pci_apb_init(hwaddr special_base, /* APB secondary busses */ pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, TYPE_PBM_PCI_BRIDGE); - br =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq); + d->bridgeB =3D PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq); qdev_init_nofail(&pci_dev->qdev); - *busB =3D pci_bridge_get_sec_bus(br); =20 pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, TYPE_PBM_PCI_BRIDGE); - br =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq); + d->bridgeA =3D PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq); qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); - *busA =3D pci_bridge_get_sec_bus(br); =20 return d; } diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 2afd3f28dd..47952befcb 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -27,6 +27,7 @@ #include "cpu.h" #include "hw/hw.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/apb.h" #include "hw/i386/pc.h" @@ -501,7 +502,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, =20 prom_init(hwdef->prom_addr, bios_name); =20 - apb =3D pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_b= usB); + apb =3D pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE); =20 /* Wire up PCI interrupts to CPU */ for (i =3D 0; i < IVEC_MAX; i++) { @@ -510,6 +511,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem, } =20 pci_bus =3D PCI_HOST_BRIDGE(apb)->bus; + pci_busA =3D pci_bridge_get_sec_bus(apb->bridgeA); + pci_busB =3D pci_bridge_get_sec_bus(apb->bridgeB); =20 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA = is reserved (leaving no slots free after on-board devices) however slo= ts diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index f7ead680f3..ae15d8ce59 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -68,6 +68,8 @@ typedef struct APBState { MemoryRegion pci_ioport; uint64_t pci_irq_in; IOMMUState iommu; + PCIBridge *bridgeA; + PCIBridge *bridgeB; uint32_t pci_control[16]; uint32_t pci_irq_map[8]; uint32_t pci_err_irq_map[4]; @@ -92,6 +94,5 @@ typedef struct PBMPCIBridge { OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) =20 APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - PCIBus **bus2, PCIBus **bus3); + hwaddr mem_base); #endif --=20 2.11.0