From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513636969861118.96493546460738; Mon, 18 Dec 2017 14:42:49 -0800 (PST) Received: from localhost ([::1]:49966 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR47F-0008Jg-HA for importer@patchew.org; Mon, 18 Dec 2017 17:42:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR45a-0007HN-D7 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eR45Z-00046m-9N for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:50 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43006) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eR45Z-0003uN-3e for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:49 -0500 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eR45P-0008D8-M3; Mon, 18 Dec 2017 23:40:39 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-000700-0p; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:25 +0100 Message-Id: <20171218224030.26726-2-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 1/6] target/sh4: add missing tcg_temp_free() in _decode_opc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 From: Philippe Mathieu-Daud=C3=A9 missed in c55497ecb8c and 852d481faf7. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20171205170013.22337-3-f4bug@amsat.org> Reviewed-by: Aurelien Jarno Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8569179883..f56808b45d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -601,6 +601,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL); tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(addr); } return; case 0x6004: /* mov.b @Rm+,Rn */ @@ -1524,6 +1525,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL); gen_helper_movcal(cpu_env, REG(B11_8), val); tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_temp_free(val); } ctx->has_movcal =3D 1; return; --=20 2.15.1 From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513637107852563.9519813496001; Mon, 18 Dec 2017 14:45:07 -0800 (PST) Received: from localhost ([::1]:50010 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR49T-0001k1-Qk for importer@patchew.org; Mon, 18 Dec 2017 17:44:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR45a-0007He-DW for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eR45Z-00046u-9V for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:50 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eR45Z-0003uc-3t; Mon, 18 Dec 2017 17:40:49 -0500 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eR45P-0008D9-Rx; Mon, 18 Dec 2017 23:40:39 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-000707-5A; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:26 +0100 Message-Id: <20171218224030.26726-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 2/6] target/sh4: fix TCG leak during gusa sequence X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-stable@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e This fixes bug #1735384 while running java under qemu-sh4. When debug was enabled it showed a problem with TCG temps. Once fixed I was able to run java -version normally. Cc: qemu-stable@nongnu.org Reported-by: John Paul Adrian Glaubitz Suggested-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-Id: <20171206093050.25308-1-alex.bennee@linaro.org> Reviewed-by: Richard Henderson Reviewed-by: Aurelien Jarno Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index f56808b45d..4a4a5c877e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2191,7 +2191,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) } =20 /* If op_src is not a valid register, then op_arg was a constant. */ - if (op_src < 0) { + if (op_src < 0 && !TCGV_IS_UNUSED(op_arg)) { tcg_temp_free_i32(op_arg); } =20 --=20 2.15.1 From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15136371113329.768141307554743; Mon, 18 Dec 2017 14:45:11 -0800 (PST) Received: from localhost ([::1]:50011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR49W-0001lf-60 for importer@patchew.org; Mon, 18 Dec 2017 17:44:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR45b-0007Ho-3n for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eR45Z-00048E-L8 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:51 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eR45Z-0003vU-Bf for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:49 -0500 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eR45Q-0008DA-3i; Mon, 18 Dec 2017 23:40:40 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-00070E-AI; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:27 +0100 Message-Id: <20171218224030.26726-4-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 3/6] target/sh4: Use cmpxchg for movco when parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , Laurent Vivier , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson Message-Id: <20170907185057.23421-2-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno --- linux-user/main.c | 19 +++++++++--- target/sh4/cpu.h | 4 ++- target/sh4/helper.c | 1 + target/sh4/translate.c | 82 ++++++++++++++++++++++++++++++++++++----------= ---- 4 files changed, 79 insertions(+), 27 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 2fd2a143ed..71696ed33d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2679,6 +2679,8 @@ void cpu_loop(CPUSH4State *env) target_siginfo_t info; =20 while (1) { + bool arch_interrupt =3D true; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); @@ -2710,13 +2712,14 @@ void cpu_loop(CPUSH4State *env) int sig; =20 sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { + if (sig) { info.si_signo =3D sig; info.si_errno =3D 0; info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + } else { + arch_interrupt =3D false; + } } break; case 0xa0: @@ -2727,9 +2730,9 @@ void cpu_loop(CPUSH4State *env) info._sifields._sigfault._addr =3D env->tea; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: printf ("Unhandled trap: 0x%x\n", trapnr); @@ -2737,6 +2740,14 @@ void cpu_loop(CPUSH4State *env) exit(EXIT_FAILURE); } process_pending_signals (env); + + /* Most of the traps imply an exception or interrupt, which + implies an REI instruction has been executed. Which means + that LDST (aka LOK_ADDR) should be cleared. But there are + a few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->lock_addr =3D -1; + } } } #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 960b46870d..a2c26e0597 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -188,7 +188,9 @@ typedef struct CPUSH4State { tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ tlb_t utlb[UTLB_SIZE]; /* unified translation table */ =20 - uint32_t ldst; + /* LDST =3D LOCK_ADDR !=3D -1. */ + uint32_t lock_addr; + uint32_t lock_value; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 28d93c2543..680b583e53 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -171,6 +171,7 @@ void superh_cpu_do_interrupt(CPUState *cs) env->spc =3D env->pc; env->sgr =3D env->gregs[15]; env->sr |=3D (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); + env->lock_addr =3D -1; =20 if (env->flags & DELAY_SLOT_MASK) { /* Branch instruction should be executed again before delay slot. = */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4a4a5c877e..f7fe1a46d8 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -69,7 +69,8 @@ static TCGv cpu_gregs[32]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; -static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; +static TCGv cpu_pr, cpu_fpscr, cpu_fpul; +static TCGv cpu_lock_addr, cpu_lock_value; static TCGv cpu_fregs[32]; =20 /* internal register indexes */ @@ -147,8 +148,12 @@ void sh4_translate_init(void) offsetof(CPUSH4State, delayed_cond), "_delayed_cond_"); - cpu_ldst =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, ldst), "_ldst_"); + cpu_lock_addr =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_addr= ), + "_lock_addr_"); + cpu_lock_value =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_val= ue), + "_lock_value_"); =20 for (i =3D 0; i < 32; i++) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -1549,31 +1554,64 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0073: /* MOVCO.L - LDST -> T - If (T =3D=3D 1) R0 -> (Rn) - 0 -> LDST - */ + * LDST -> T + * If (T =3D=3D 1) R0 -> (Rn) + * 0 -> LDST + * + * The above description doesn't work in a parallel context. + * Since we currently support no smp boards, this implies user-mod= e. + * But we can still support the official mechanism while user-mode + * is single-threaded. */ CHECK_SH4A { - TCGLabel *label =3D gen_new_label(); - tcg_gen_mov_i32(cpu_sr_t, cpu_ldst); - tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); - gen_set_label(label); - tcg_gen_movi_i32(cpu_ldst, 0); - return; + TCGLabel *fail =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + if ((tb_cflags(ctx->tb) & CF_PARALLEL)) { + TCGv tmp; + + tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), + cpu_lock_addr, fail); + tmp =3D tcg_temp_new(); + tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, + REG(0), ctx->memidx, MO_TEUL); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_v= alue); + tcg_temp_free(tmp); + } else { + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail); + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TE= UL); + tcg_gen_movi_i32(cpu_sr_t, 1); + } + tcg_gen_br(done); + + gen_set_label(fail); + tcg_gen_movi_i32(cpu_sr_t, 0); + + gen_set_label(done); + tcg_gen_movi_i32(cpu_lock_addr, -1); } + return; case 0x0063: /* MOVLI.L @Rm,R0 - 1 -> LDST - (Rm) -> R0 - When interrupt/exception - occurred 0 -> LDST - */ + * 1 -> LDST + * (Rm) -> R0 + * When interrupt/exception + * occurred 0 -> LDST + * + * In a parallel context, we must also save the loaded value + * for use with the cmpxchg that we'll use with movco.l. */ CHECK_SH4A - tcg_gen_movi_i32(cpu_ldst, 0); - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); - tcg_gen_movi_i32(cpu_ldst, 1); + if ((tb_cflags(ctx->tb) & CF_PARALLEL)) { + TCGv tmp =3D tcg_temp_new(); + tcg_gen_mov_i32(tmp, REG(B11_8)); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_mov_i32(cpu_lock_value, REG(0)); + tcg_gen_mov_i32(cpu_lock_addr, tmp); + tcg_temp_free(tmp); + } else { + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_movi_i32(cpu_lock_addr, 0); + } return; case 0x0093: /* ocbi @Rn */ { --=20 2.15.1 From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513636969991923.292719626391; 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Mon, 18 Dec 2017 23:40:40 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-00070L-Dl; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:28 +0100 Message-Id: <20171218224030.26726-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 4/6] target/sh4: Convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20170907185057.23421-3-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 65 +++++++++++++++++++++++-----------------------= ---- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index f7fe1a46d8..efd1081c57 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -25,10 +25,9 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" =20 @@ -39,7 +38,7 @@ typedef struct DisasContext { uint16_t opcode; uint32_t tbflags; /* should stay unmodified during the TB translati= on */ uint32_t envflags; /* should stay in sync with env->flags using TCG = ops */ - int bstate; + DisasJumpType bstate; int memidx; int gbank; int fbank; @@ -55,14 +54,10 @@ typedef struct DisasContext { #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) #endif =20 -enum { - BS_NONE =3D 0, /* We go out of the TB without reaching a branch or= an - * exception condition - */ - BS_STOP =3D 1, /* We want to stop translation for any reason */ - BS_BRANCH =3D 2, /* We reached a branch condition */ - BS_EXCP =3D 3, /* We reached an exception condition */ -}; +/* Target-specific values for ctx->bstate. */ +/* We want to exit back to the cpu loop for some reason. + Usually this is to recognize interrupts immediately. */ +#define DISAS_STOP DISAS_TARGET_0 =20 /* global register indexes */ static TCGv cpu_gregs[32]; @@ -258,6 +253,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) tcg_gen_lookup_and_goto_ptr(); } } + ctx->bstate =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext * ctx) @@ -304,7 +300,7 @@ static void gen_conditional_jump(DisasContext *ctx, tar= get_ulong dest, gen_goto_tb(ctx, 0, dest); gen_set_label(l1); gen_goto_tb(ctx, 1, ctx->pc + 2); - ctx->bstate =3D BS_BRANCH; + ctx->bstate =3D DISAS_NORETURN; } =20 /* Delayed conditional jump (bt or bf) */ @@ -327,6 +323,7 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) gen_jump(ctx); =20 gen_set_label(l1); + ctx->bstate =3D DISAS_NEXT; return; } =20 @@ -468,7 +465,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->envflags |=3D DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x0058: /* sets */ tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); @@ -479,17 +476,17 @@ static void _decode_opc(DisasContext * ctx) case 0xfbfd: /* frchg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0xf3fd: /* fschg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0xf7fd: /* fpchg */ CHECK_SH4A tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x0009: /* nop */ return; @@ -524,7 +521,7 @@ static void _decode_opc(DisasContext * ctx) region (stored in R0) in the next TB. */ if (B11_8 =3D=3D 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARAL= LEL)) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } #endif tcg_gen_movi_i32(REG(B11_8), B7_0s); @@ -1310,7 +1307,7 @@ static void _decode_opc(DisasContext * ctx) imm =3D tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); tcg_temp_free(imm); - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; } return; case 0xc800: /* tst #imm,R0 */ @@ -1419,7 +1416,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); gen_write_sr(val); tcg_temp_free(val); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x4007: /* ldc.l @Rm+,SR */ @@ -1431,7 +1428,7 @@ static void _decode_opc(DisasContext * ctx) gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x0002: /* stc SR,Rn */ @@ -1493,7 +1490,7 @@ static void _decode_opc(DisasContext * ctx) case 0x406a: /* lds Rm,FPSCR */ CHECK_FPU_ENABLED gen_helper_ld_fpscr(cpu_env, REG(B11_8)); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x4066: /* lds.l @Rm+,FPSCR */ CHECK_FPU_ENABLED @@ -1503,7 +1500,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); tcg_temp_free(addr); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x006a: /* sts FPSCR,Rn */ @@ -1841,7 +1838,7 @@ static void _decode_opc(DisasContext * ctx) gen_save_cpu_state(ctx, true); gen_helper_raise_illegal_instruction(cpu_env); } - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; return; =20 do_fpu_disabled: @@ -1851,7 +1848,7 @@ static void _decode_opc(DisasContext * ctx) } else { gen_helper_raise_fpu_disable(cpu_env); } - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; return; } =20 @@ -1877,7 +1874,6 @@ static void decode_opc(DisasContext * ctx) ctx->envflags &=3D ~GUSA_MASK; =20 tcg_gen_movi_i32(cpu_flags, ctx->envflags); - ctx->bstate =3D BS_BRANCH; if (old_flags & DELAY_SLOT_CONDITIONAL) { gen_delayed_conditional_jump(ctx); } else { @@ -2248,7 +2244,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; =20 /* We're not executing an instruction, but we must report one for the purposes of accounting within the TB. We might as well report the @@ -2271,7 +2267,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) ctx.pc =3D pc_start; ctx.tbflags =3D (uint32_t)tb->flags; ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.bstate =3D BS_NONE; + ctx.bstate =3D DISAS_NEXT; ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ @@ -2309,7 +2305,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) } #endif =20 - while (ctx.bstate =3D=3D BS_NONE + while (ctx.bstate =3D=3D DISAS_NEXT && num_insns < max_insns && !tcg_op_buf_full()) { tcg_gen_insn_start(ctx.pc, ctx.envflags); @@ -2319,7 +2315,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* We have hit a breakpoint - make sure PC is up-to-date */ gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); - ctx.bstate =3D BS_EXCP; + ctx.bstate =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -2350,19 +2346,18 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) gen_helper_debug(cpu_env); } else { switch (ctx.bstate) { - case BS_STOP: + case DISAS_STOP: gen_save_cpu_state(&ctx, true); tcg_gen_exit_tb(0); break; - case BS_NONE: + case DISAS_NEXT: gen_save_cpu_state(&ctx, false); gen_goto_tb(&ctx, 0, ctx.pc); break; - case BS_EXCP: - /* fall through */ - case BS_BRANCH: - default: + case DISAS_NORETURN: break; + default: + g_assert_not_reached(); } } =20 --=20 2.15.1 From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151363727063261.805660045824425; Mon, 18 Dec 2017 14:47:50 -0800 (PST) Received: from localhost ([::1]:50193 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR4C6-0003sy-BE for importer@patchew.org; Mon, 18 Dec 2017 17:47:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR45a-0007Hj-HI for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eR45Z-00047n-I3 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:50 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43026) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eR45Z-0003vY-Bi for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:49 -0500 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eR45Q-0008DC-9x; Mon, 18 Dec 2017 23:40:40 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-00070S-H3; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:29 +0100 Message-Id: <20171218224030.26726-6-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 5/6] target/sh4: Do not singlestep after exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson If we've already raised an exception (and set NORETURN), do not emit unreachable code to raise a debug exception. Note that gen_goto_tb takes single-stepping into account. Signed-off-by: Richard Henderson Message-Id: <20170907185057.23421-4-richard.henderson@linaro.org> Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index efd1081c57..dd9aaa4e63 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -270,6 +270,7 @@ static void gen_jump(DisasContext * ctx) } else { tcg_gen_lookup_and_goto_ptr(); } + ctx->bstate =3D DISAS_NORETURN; } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); } @@ -2341,24 +2342,23 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.envflags &=3D ~GUSA_MASK; } =20 - if (cs->singlestep_enabled) { + switch (ctx.bstate) { + case DISAS_STOP: gen_save_cpu_state(&ctx, true); - gen_helper_debug(cpu_env); - } else { - switch (ctx.bstate) { - case DISAS_STOP: - gen_save_cpu_state(&ctx, true); + if (cs->singlestep_enabled) { + gen_helper_debug(cpu_env); + } else { tcg_gen_exit_tb(0); - break; - case DISAS_NEXT: - gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.pc); - break; - case DISAS_NORETURN: - break; - default: - g_assert_not_reached(); - } + } + break; + case DISAS_NEXT: + gen_save_cpu_state(&ctx, false); + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); } =20 gen_tb_end(tb, num_insns); --=20 2.15.1 From nobody Tue Oct 28 04:13:15 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513637111442886.5825212428134; Mon, 18 Dec 2017 14:45:11 -0800 (PST) Received: from localhost ([::1]:50012 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR49b-0001p4-SO for importer@patchew.org; Mon, 18 Dec 2017 17:44:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR45c-0007IB-6X for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eR45Z-00048M-Lx for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:52 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eR45Z-0003vZ-BF for qemu-devel@nongnu.org; Mon, 18 Dec 2017 17:40:49 -0500 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eR45Q-0008DE-C8; Mon, 18 Dec 2017 23:40:40 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.90_RC3) (envelope-from ) id 1eR45P-00070Z-KA; Mon, 18 Dec 2017 23:40:39 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 23:40:30 +0100 Message-Id: <20171218224030.26726-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218224030.26726-1-aurelien@aurel32.net> References: <20171218224030.26726-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 6/6] target/sh4: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson [aurel32: fix whitespace] Message-Id: <20170907185057.23421-5-richard.henderson@linaro.org> Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 154 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 78 insertions(+), 76 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index dd9aaa4e63..038663cc05 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -33,19 +33,19 @@ =20 =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc; - uint16_t opcode; - uint32_t tbflags; /* should stay unmodified during the TB translati= on */ - uint32_t envflags; /* should stay in sync with env->flags using TCG = ops */ - DisasJumpType bstate; + DisasContextBase base; + + uint32_t tbflags; /* should stay unmodified during the TB translation= */ + uint32_t envflags; /* should stay in sync with env->flags using TCG op= s */ int memidx; int gbank; int fbank; uint32_t delayed_pc; - int singlestep_enabled; uint32_t features; - int has_movcal; + + uint16_t opcode; + + bool has_movcal; } DisasContext; =20 #if defined(CONFIG_USER_ONLY) @@ -54,7 +54,7 @@ typedef struct DisasContext { #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) #endif =20 -/* Target-specific values for ctx->bstate. */ +/* Target-specific values for ctx->base.is_jmp. */ /* We want to exit back to the cpu loop for some reason. Usually this is to recognize interrupts immediately. */ #define DISAS_STOP DISAS_TARGET_0 @@ -209,7 +209,7 @@ static void gen_write_sr(TCGv src) static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) { if (save_pc) { - tcg_gen_movi_i32(cpu_pc, ctx->pc); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); } if (ctx->delayed_pc !=3D (uint32_t) -1) { tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); @@ -227,11 +227,11 @@ static inline bool use_exit_tb(DisasContext *ctx) static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Use a direct jump if in same page and singlestep not enabled */ - if (unlikely(ctx->singlestep_enabled || use_exit_tb(ctx))) { + if (unlikely(ctx->base.singlestep_enabled || use_exit_tb(ctx))) { return false; } #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -242,10 +242,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + n); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n); } else { tcg_gen_movi_i32(cpu_pc, dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); @@ -253,7 +253,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) tcg_gen_lookup_and_goto_ptr(); } } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext * ctx) @@ -263,14 +263,14 @@ static void gen_jump(DisasContext * ctx) delayed jump as immediate jump are conditinal jumps */ tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); tcg_gen_discard_i32(cpu_delayed_pc); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); } @@ -300,8 +300,8 @@ static void gen_conditional_jump(DisasContext *ctx, tar= get_ulong dest, tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); gen_goto_tb(ctx, 0, dest); gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->pc + 2); - ctx->bstate =3D DISAS_NORETURN; + gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 /* Delayed conditional jump (bt or bf) */ @@ -324,12 +324,12 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) gen_jump(ctx); =20 gen_set_label(l1); - ctx->bstate =3D DISAS_NEXT; + ctx->base.is_jmp =3D DISAS_NEXT; return; } =20 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); - gen_goto_tb(ctx, 1, ctx->pc + 2); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); gen_set_label(l1); gen_jump(ctx); } @@ -466,7 +466,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->envflags |=3D DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x0058: /* sets */ tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); @@ -477,23 +477,23 @@ static void _decode_opc(DisasContext * ctx) case 0xfbfd: /* frchg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0xf3fd: /* fschg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0xf7fd: /* fpchg */ CHECK_SH4A tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x0009: /* nop */ return; case 0x001b: /* sleep */ CHECK_PRIVILEGED - tcg_gen_movi_i32(cpu_pc, ctx->pc + 2); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2); gen_helper_sleep(cpu_env); return; } @@ -520,23 +520,24 @@ static void _decode_opc(DisasContext * ctx) /* Detect the start of a gUSA region. If so, update envflags and end the TB. This will allow us to see the end of the region (stored in R0) in the next TB. */ - if (B11_8 =3D=3D 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARAL= LEL)) { + if (B11_8 =3D=3D 15 && B7_0s < 0 && + (tb_cflags(ctx->base.tb) & CF_PARALLEL)) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } #endif tcg_gen_movi_i32(REG(B11_8), B7_0s); return; case 0x9000: /* mov.w @(disp,PC),Rn */ { - TCGv addr =3D tcg_const_i32(ctx->pc + 4 + B7_0 * 2); + TCGv addr =3D tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); tcg_temp_free(addr); } return; case 0xd000: /* mov.l @(disp,PC),Rn */ { - TCGv addr =3D tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); + TCGv addr =3D tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4)= & ~3); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); tcg_temp_free(addr); } @@ -546,13 +547,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0xa000: /* bra disp */ CHECK_NOT_DELAY_SLOT - ctx->delayed_pc =3D ctx->pc + 4 + B11_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; ctx->envflags |=3D DELAY_SLOT; return; case 0xb000: /* bsr disp */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); - ctx->delayed_pc =3D ctx->pc + 4 + B11_0s * 2; + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; ctx->envflags |=3D DELAY_SLOT; return; } @@ -1180,22 +1181,22 @@ static void _decode_opc(DisasContext * ctx) return; case 0x8b00: /* bf label */ CHECK_NOT_DELAY_SLOT - gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, false); + gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, false= ); return; case 0x8f00: /* bf/s label */ CHECK_NOT_DELAY_SLOT tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1); - ctx->delayed_pc =3D ctx->pc + 4 + B7_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; return; case 0x8900: /* bt label */ CHECK_NOT_DELAY_SLOT - gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, true); + gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, true); return; case 0x8d00: /* bt/s label */ CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t); - ctx->delayed_pc =3D ctx->pc + 4 + B7_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; return; case 0x8800: /* cmp/eq #imm,R0 */ @@ -1282,7 +1283,8 @@ static void _decode_opc(DisasContext * ctx) } return; case 0xc700: /* mova @(disp,PC),R0 */ - tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); + tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + + 4 + B7_0 * 4) & ~3); return; case 0xcb00: /* or #imm,R0 */ tcg_gen_ori_i32(REG(0), REG(0), B7_0); @@ -1308,7 +1310,7 @@ static void _decode_opc(DisasContext * ctx) imm =3D tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); tcg_temp_free(imm); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } return; case 0xc800: /* tst #imm,R0 */ @@ -1376,13 +1378,13 @@ static void _decode_opc(DisasContext * ctx) switch (ctx->opcode & 0xf0ff) { case 0x0023: /* braf Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); + tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4= ); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x0003: /* bsrf Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; @@ -1405,7 +1407,7 @@ static void _decode_opc(DisasContext * ctx) return; case 0x400b: /* jsr @Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; @@ -1417,7 +1419,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); gen_write_sr(val); tcg_temp_free(val); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x4007: /* ldc.l @Rm+,SR */ @@ -1429,7 +1431,7 @@ static void _decode_opc(DisasContext * ctx) gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x0002: /* stc SR,Rn */ @@ -1491,7 +1493,7 @@ static void _decode_opc(DisasContext * ctx) case 0x406a: /* lds Rm,FPSCR */ CHECK_FPU_ENABLED gen_helper_ld_fpscr(cpu_env, REG(B11_8)); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x4066: /* lds.l @Rm+,FPSCR */ CHECK_FPU_ENABLED @@ -1501,7 +1503,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); tcg_temp_free(addr); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x006a: /* sts FPSCR,Rn */ @@ -1565,7 +1567,7 @@ static void _decode_opc(DisasContext * ctx) TCGLabel *fail =3D gen_new_label(); TCGLabel *done =3D gen_new_label(); =20 - if ((tb_cflags(ctx->tb) & CF_PARALLEL)) { + if ((tb_cflags(ctx->base.tb) & CF_PARALLEL)) { TCGv tmp; =20 tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), @@ -1599,7 +1601,7 @@ static void _decode_opc(DisasContext * ctx) * In a parallel context, we must also save the loaded value * for use with the cmpxchg that we'll use with movco.l. */ CHECK_SH4A - if ((tb_cflags(ctx->tb) & CF_PARALLEL)) { + if ((tb_cflags(ctx->base.tb) & CF_PARALLEL)) { TCGv tmp =3D tcg_temp_new(); tcg_gen_mov_i32(tmp, REG(B11_8)); tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); @@ -1827,7 +1829,7 @@ static void _decode_opc(DisasContext * ctx) } #if 0 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", - ctx->opcode, ctx->pc); + ctx->opcode, ctx->base.pc_next); fflush(stderr); #endif do_illegal: @@ -1839,7 +1841,7 @@ static void _decode_opc(DisasContext * ctx) gen_save_cpu_state(ctx, true); gen_helper_raise_illegal_instruction(cpu_env); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return; =20 do_fpu_disabled: @@ -1849,7 +1851,7 @@ static void _decode_opc(DisasContext * ctx) } else { gen_helper_raise_fpu_disable(cpu_env); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return; } =20 @@ -1901,8 +1903,8 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) int mv_src, mt_dst, st_src, st_mop; TCGv op_arg; =20 - uint32_t pc =3D ctx->pc; - uint32_t pc_end =3D ctx->tb->cs_base; + uint32_t pc =3D ctx->base.pc_next; + uint32_t pc_end =3D ctx->base.tb->cs_base; int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); int max_insns =3D (pc_end - pc) / 2; int i; @@ -2232,7 +2234,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) =20 /* The entire region has been translated. */ ctx->envflags &=3D ~GUSA_MASK; - ctx->pc =3D pc_end; + ctx->base.pc_next =3D pc_end; return max_insns; =20 fail: @@ -2245,13 +2247,13 @@ static int decode_gusa(DisasContext *ctx, CPUSH4Sta= te *env, int *pmax_insns) ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 /* We're not executing an instruction, but we must report one for the purposes of accounting within the TB. We might as well report the - entire region consumed via ctx->pc so that it's immediately availab= le - in the disassembly dump. */ - ctx->pc =3D pc_end; + entire region consumed via ctx->base.pc_next so that it's immediate= ly + available in the disassembly dump. */ + ctx->base.pc_next =3D pc_end; return 1; } #endif @@ -2265,16 +2267,16 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) int max_insns; =20 pc_start =3D tb->pc; - ctx.pc =3D pc_start; + ctx.base.pc_next =3D pc_start; ctx.tbflags =3D (uint32_t)tb->flags; ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.bstate =3D DISAS_NEXT; + ctx.base.is_jmp =3D DISAS_NEXT; ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && @@ -2289,11 +2291,11 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ - num_insns =3D -(ctx.pc | TARGET_PAGE_MASK) / 2; + num_insns =3D -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2; max_insns =3D MIN(max_insns, num_insns); =20 /* Single stepping means just that. */ - if (ctx.singlestep_enabled || singlestep) { + if (ctx.base.singlestep_enabled || singlestep) { max_insns =3D 1; } =20 @@ -2306,22 +2308,22 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) } #endif =20 - while (ctx.bstate =3D=3D DISAS_NEXT + while (ctx.base.is_jmp =3D=3D DISAS_NEXT && num_insns < max_insns && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.pc, ctx.envflags); + tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { /* We have hit a breakpoint - make sure PC is up-to-date */ gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); - ctx.bstate =3D DISAS_NORETURN; + ctx.base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.pc +=3D 2; + ctx.base.pc_next +=3D 2; break; } =20 @@ -2329,9 +2331,9 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) gen_io_start(); } =20 - ctx.opcode =3D cpu_lduw_code(env, ctx.pc); + ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); decode_opc(&ctx); - ctx.pc +=3D 2; + ctx.base.pc_next +=3D 2; } if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); @@ -2342,10 +2344,10 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.envflags &=3D ~GUSA_MASK; } =20 - switch (ctx.bstate) { + switch (ctx.base.is_jmp) { case DISAS_STOP: gen_save_cpu_state(&ctx, true); - if (cs->singlestep_enabled) { + if (ctx.base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(0); @@ -2353,7 +2355,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) break; case DISAS_NEXT: gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.pc); + gen_goto_tb(&ctx, 0, ctx.base.pc_next); break; case DISAS_NORETURN: break; @@ -2363,7 +2365,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 gen_tb_end(tb, num_insns); =20 - tb->size =3D ctx.pc - pc_start; + tb->size =3D ctx.base.pc_next - pc_start; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS @@ -2371,7 +2373,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.pc - pc_start); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); qemu_log("\n"); qemu_log_unlock(); } --=20 2.15.1