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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k8F0HjW9dFA0ovtDS/CZjiEOnmVa5Jw57Xx7i6w7EhA=; b=Rua+aG9oZv539Nr+S7cb4QQctCvYIN6UazkxzjzNI1elClLXMdtg5TuzQVZaTphbdY WgLGQdb/8yPG3kkVW6VO4wKYL7gLIMV7yeusMiPMJatsmu5uDukYnttvQ5/ym/c9Drsx d1HhapimgdhwwPN6gmHp05weNJCEC/Mw0SHUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k8F0HjW9dFA0ovtDS/CZjiEOnmVa5Jw57Xx7i6w7EhA=; b=Bgdmu+OxM7wpXWHtuyViEpNKZXxl8NGwBrbAzJZO2XanpvtyJlcnYLLyYuIJ4aifu4 oy0WHoCoejoGcRODe5goJaNDtAkJOGwI909vdmQIj8FFge65EswEoIDd4LmLfuZ96Wfm KEgLzoB7MC5zfYNepmGmStu1Lk7nSJ9flfx0NGU6FLlwwKI8PoUDMevh8ampIP0JfZTN MjjUpRM2DGahXCrWHoK8C5rY4CJOzjNYcHXmEqJDXgqM6iFTkfABMqhG+p9VXKt9f0Jt Ut8Wttbgpj6nhmGO5zo033eQH6B2hqR7by9qRrEMDhibCg29ywQhTlqbLoF8V45XcwUA howg== X-Gm-Message-State: AKGB3mL/t/Yi/1r5vUmqjGkTznLDWyQycGLtbrMAFro1Yv9/k1g9D06b A1EIJ5OMSlSQyXWRKIdvTsrlWw3pV+8= X-Google-Smtp-Source: ACJfBouKufQhxjGdaeibSgpVYPQYI1XOP6Nqlt8wdIa2ncDmHAW1KXONkvd0/6dh6MFUbYK8DGPgMA== X-Received: by 10.99.132.195 with SMTP id k186mr447536pgd.130.1513619167266; Mon, 18 Dec 2017 09:46:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:37 -0800 Message-Id: <20171218174552.18871-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 08/23] target/arm: Handle SVE registers in write_fp_dreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When storing to an AdvSIMD FP register, all of the high bits of the SVE register are zeroed. At the same time, export the function for use in translate-sve.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 32 ++++++++++++++++++-------------- 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9014b5bf8b..07861fa9c6 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -35,6 +35,7 @@ TCGv_i64 cpu_reg(DisasContext *s, int reg); TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); +void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8be1660661..b951045820 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -533,13 +533,28 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 -static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) +/* Clear the bits above an 64-bit vector. + * If SVE is not enabled, then there are only 128 bits in the vector. + */ +static void clear_vec_high(DisasContext *s, int rd) { + unsigned ofs =3D fp_reg_offset(s, rd, MO_64); + unsigned vsz =3D vec_full_reg_size(s); TCGv_i64 tcg_zero =3D tcg_const_i64(0); =20 - tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); - tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); + tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); tcg_temp_free_i64(tcg_zero); + if (vsz > 16) { + tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0); + } +} + +void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) +{ + unsigned ofs =3D fp_reg_offset(s, reg, MO_64); + + tcg_gen_st_i64(v, cpu_env, ofs); + clear_vec_high(s, reg); } =20 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) @@ -1015,17 +1030,6 @@ static void write_vec_element_i32(DisasContext *s, T= CGv_i32 tcg_src, } } =20 -/* Clear the high 64 bits of a 128 bit vector (in general non-quad - * vector ops all need to do this). - */ -static void clear_vec_high(DisasContext *s, int rd) -{ - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - write_vec_element(s, tcg_zero, rd, 1, MO_64); - tcg_temp_free_i64(tcg_zero); -} - /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, TCGv_i64 tcg_addr, int size) --=20 2.14.3