From nobody Tue Oct 28 21:11:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513623632719520.7218099652652; Mon, 18 Dec 2017 11:00:32 -0800 (PST) Received: from localhost ([::1]:55169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR0eK-00026o-Gy for importer@patchew.org; Mon, 18 Dec 2017 14:00:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQzUm-0008WJ-9r for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eQzUk-0002Mn-5Z for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:32 -0500 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:41953) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eQzUk-0002LB-0v for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:30 -0500 Received: by mail-pl0-x243.google.com with SMTP id g2so5248770pli.8 for ; Mon, 18 Dec 2017 09:46:29 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-7-63.tukw.qwest.net. [174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hy9sfhMkBpSM5NImxVV6CJzkqzQztXElQhyddscya8E=; b=js5CcSy/+ldsVuSGma86YoKPXqco6HnLHfqma6ID6qBym4j1UumxmNZaGd1+jsYO8L ya30embRUCOFxxpeOU6NJQj5/L/xhzwjv4Mm9ejP4khGSu+QUPWo/V7aDDVKEnjlef4N dU5apt02G1VB4r02hH2Fs9fO+TyKGMkgssiZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hy9sfhMkBpSM5NImxVV6CJzkqzQztXElQhyddscya8E=; b=CY1XXSMZFOCciAOijRfkoD3sbz+T0uA9YBEZR4PaVGjPETmBAIDKsNMZhLU9X0YZew rZWsySGd07oZbNAcMCgxTXgTxbjlyPIBLxfLNcaPO+fjZdmMhAEA9pfDp6ywOvHw4f3D HeO+R1atkyLSbjKk+re4jou1nAHZMDQG2DKbHVJFoTEiRfxPdCj25Tai/+BxBA8PBl53 tTRYnCPL+Cg6WUXnA0O8XViLSbY+W0M9UCWEPiAlLEABcDP0CDPvtQ9qEjza1qq41ypf tig1Y0xDrTlFxb5O6s6Zs5RAeR1vR32zlyjMpNio/GsRMN3lB2SgwMMn3Fz/YkbtDPig vIAA== X-Gm-Message-State: AKGB3mJrRF843BenPAQy334l26e6qgLXur3WYyfzcvo5sVXgiXnsijbG n2CU0IbcS8JAA5avtsucNHQZnuA27u0= X-Google-Smtp-Source: ACJfBovOwLEmh0uzQhDh3yd+yNSU54dafo5qzarLKoXrHW4Qy8+QHdbvtxiUKY4IMg9zlfyQttvqHA== X-Received: by 10.84.129.7 with SMTP id 7mr512016plb.104.1513619188594; Mon, 18 Dec 2017 09:46:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:51 -0800 Message-Id: <20171218174552.18871-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 22/23] target/arm: Implement SVE floating-point trig select coefficient X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 4 ++++ target/arm/sve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 19 +++++++++++++++++++ target/arm/sve.def | 3 +++ 4 files changed, 68 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index c72ae3390f..ccf5405d63 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -383,6 +383,10 @@ DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 936a6ec648..5341f6d0e5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1104,6 +1104,48 @@ void HELPER(sve_fexpa_d)(void *vd, void *vn, uint32_= t desc) } } =20 +void HELPER(sve_ftssel_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 2; + uint16_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint16_t nn =3D n[i]; + uint16_t mm =3D m[i]; + if (mm & 1) { + nn =3D float16_one; + } + d[i] =3D nn ^ (mm & 2) << 14; + } +} + +void HELPER(sve_ftssel_s)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint32_t nn =3D n[i]; + uint32_t mm =3D m[i]; + if (mm & 1) { + nn =3D float32_one; + } + d[i] =3D nn ^ (mm & 2) << 30; + } +} + +void HELPER(sve_ftssel_d)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + uint64_t nn =3D n[i]; + uint64_t mm =3D m[i]; + if (mm & 1) { + nn =3D float64_one; + } + d[i] =3D nn ^ (mm & 2) << 62; + } +} + void HELPER(sve_ldr)(CPUARMState *env, void *d, target_ulong addr, uint32_= t len) { intptr_t i, len_align =3D QEMU_ALIGN_DOWN(len, 8); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b671462611..a6c31e0e9c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -757,6 +757,25 @@ void trans_FEXPA(DisasContext *s, arg_rr_esz *a, uint3= 2_t insn) vsz, vsz, 0, fns[a->esz]); } =20 +void trans_FTSSEL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + NULL, + gen_helper_sve_ftssel_h, + gen_helper_sve_ftssel_s, + gen_helper_sve_ftssel_d, + }; + unsigned vsz =3D size_for_gvec(vec_full_reg_size(s)); + if (a->esz =3D=3D 0) { + unallocated_encoding(s); + return; + } + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, 0, fns[a->esz]); +} + static uint64_t pred_esz_mask[4] =3D { 0xffffffffffffffffull, 0x5555555555555555ull, 0x1111111111111111ull, 0x0101010101010101ull diff --git a/target/arm/sve.def b/target/arm/sve.def index c0fc8b7665..df2730eb73 100644 --- a/target/arm/sve.def +++ b/target/arm/sve.def @@ -272,6 +272,9 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_= rn_msz_rm # SVE floating-point exponential accelerator FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn_esz # Note size != =3D 0 =20 +# SVE floating-point trig select coefficient +FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm_esz # Note size= !=3D 0 + ### SVE Predicate Generation Group =20 # SVE initialize predicate (PTRUE, PTRUES) --=20 2.14.3