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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ac6B4fIbk1rKjOWjF4fPb2HPxUZ3ZPd87nYhLxcCz84=; b=jdxcqv0gdfDRioz0IuhcUEbGXvN7sMaOlGt5J5U6PwEZhtDV9TM1ERdLldEvgf3Be2 PKUnGaQuZAfEiXrK3X3nnSODFDy9v13WblLyS+NuBAJ8H/ATu0j7CnfT9j1NPKW1kTwK AAzPYVbzEXo9lF13ZoMeNDXbAmpOZY+9JlmXg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ac6B4fIbk1rKjOWjF4fPb2HPxUZ3ZPd87nYhLxcCz84=; b=tt3Iyaj5u85087ck+LCtFjNDAW6QhhqamBND5x2phTxmBwT/NlD7PWMvMh+M0EtpSS 240a2HFZo76tvwBYIAiuoTbJZmRF54VyDoUobTTvvzMPOX+nlzPC1qYI10rSXEqbZ8pZ KS664NSnzud9OcT2qmINoJGB+P2pJUex9UR2QG7JtfCOhd4y61ryWA2vRUt8DFSLz/EY XYHftH0lRbY85mtfUqI8JsNA87sDuMPpow+nEoZtg8yj9CVcuhPt8EjAtRdHb/K8/P69 25E9xnf79LhvAuMmHnmJhnnC38NzpU9EHqqrz2hj3+QtT6utaF1OvOImrCxn7lfNYEyW UX/g== X-Gm-Message-State: AKGB3mIuPkp1Vj88LvadJ1pSWGFwaVYtZZi+pCt6EFNpk7jkZcZT9SRl C0quOcCorRNj0hVGn/zsXjiEcwaS3bg= X-Google-Smtp-Source: ACJfBotTIr17X9F9Kk5ZqY57QOGD7pG54k2Kdda6pryfFJozXMacqP1NifoWaQe5siCSTVXt+oS7vg== X-Received: by 10.98.224.200 with SMTP id d69mr497613pfm.100.1513619185256; Mon, 18 Dec 2017 09:46:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:49 -0800 Message-Id: <20171218174552.18871-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 20/23] target/arm: Implement SVE Compute Vector Address Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 5 +++++ target/arm/sve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 29 +++++++++++++++++++++++++++++ target/arm/sve.def | 12 ++++++++++++ 4 files changed, 86 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index c0e23e7a83..a9fcf25b95 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -374,6 +374,11 @@ DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, voi= d, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) =20 +DEF_HELPER_FLAGS_4(sve_adr_p32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index b6aca18d22..33b3c3432d 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -983,6 +983,46 @@ void HELPER(sve_index_d)(void *vd, uint64_t start, } } =20 +void HELPER(sve_adr_p32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 4; + uint32_t sh =3D simd_data(desc); + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + (m[i] << sh); + } +} + +void HELPER(sve_adr_p64)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + (m[i] << sh); + } +} + +void HELPER(sve_adr_s32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + ((uint64_t)(int32_t)m[i] << sh); + } +} + +void HELPER(sve_adr_u32)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t sh =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D n[i] + ((uint64_t)(uint32_t)m[i] << sh); + } +} + void HELPER(sve_ldr)(CPUARMState *env, void *d, target_ulong addr, uint32_= t len) { intptr_t i, len_align =3D QEMU_ALIGN_DOWN(len, 8); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d8e7cc7570..fcb5c4929e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -710,6 +710,35 @@ DO_ZZW(LSL, lsl) =20 #undef DO_ZZW =20 +static void do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) +{ + unsigned vsz =3D size_for_gvec(vec_full_reg_size(s)); + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, a->imm, fn); +} + +void trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + do_adr(s, a, gen_helper_sve_adr_p32); +} + +void trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + do_adr(s, a, gen_helper_sve_adr_p64); +} + +void trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + do_adr(s, a, gen_helper_sve_adr_s32); +} + +void trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn) +{ + do_adr(s, a, gen_helper_sve_adr_u32); +} + static uint64_t pred_esz_mask[4] =3D { 0xffffffffffffffffull, 0x5555555555555555ull, 0x1111111111111111ull, 0x0101010101010101ull diff --git a/target/arm/sve.def b/target/arm/sve.def index 9caed8fc66..66a88f59bc 100644 --- a/target/arm/sve.def +++ b/target/arm/sve.def @@ -47,6 +47,7 @@ # instruction patterns. =20 &rri rd rn imm +&rrri rd rn rm imm &rri_esz rd rn imm esz &rrr_esz rd rn rm esz &rpr_esz rd pg rn esz @@ -65,6 +66,9 @@ # Three operand with unused vector element size @rd_rn_rm ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=3D0 =20 +# Three operand with "memory" size, aka immediate left shift +@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri + # Three prediate operand, with governing predicate, unused vector element = size @pd_pg_pn_pm ........ .... rm:4 .. pg:4 . rn:4 . rd:4 &rprr_esz esz=3D0 =20 @@ -251,6 +255,14 @@ ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd= _rn_rm_esz # Note size !=3D LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm_esz # Note si= ze !=3D 3 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm_esz # Note si= ze !=3D 3 =20 +### SVE Compute Vector Address Group + +# SVE vector address generation +ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm +ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm +ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm +ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm + ### SVE Predicate Generation Group =20 # SVE initialize predicate (PTRUE, PTRUES) --=20 2.14.3