From nobody Tue Oct 28 21:08:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513623423617583.1647371324365; Mon, 18 Dec 2017 10:57:03 -0800 (PST) Received: from localhost ([::1]:54711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR0an-0006Wv-8J for importer@patchew.org; Mon, 18 Dec 2017 13:56:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQzUh-0008SR-1e for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eQzUf-0002GB-IW for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:27 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:38711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eQzUf-0002Fc-An for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:25 -0500 Received: by mail-pg0-x244.google.com with SMTP id f12so9433645pgo.5 for ; Mon, 18 Dec 2017 09:46:25 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-7-63.tukw.qwest.net. [174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eh9/WnyrV/yK2DjsUOEgKf0P6VP8p4vqDCBDRPGgVy0=; b=aJXwTcQyLFo35AYd0z7pfuX5ltwmussNGFBhZEBo+i/NNTRcDdtVC5ORRQnMM61UJY i+BWmUH2FHAKbP+Dzo0qSenuF4/mi3sTwe4zOdMDIzgdTU6N8P0IZ44wcEYEy35gT5q5 /5BJiwmC33lnyyDnUHq19324GFNQdEvno4lTI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eh9/WnyrV/yK2DjsUOEgKf0P6VP8p4vqDCBDRPGgVy0=; b=qNyY+qTHSYAp93D7xTtOnaUCk3OwlMRHaNhjG5AxReYFg9pPROP3FdEQFNvA6EgoB/ pK4HOc6EcV/34V/EVWJ2B0DZm+BlYhY0bPEXC+yyQ1qrRxPH8z84hvHyp8r6HZacKHNS EuYlTwA5gipJjimuJHpa3iREmo2nV1cr8z5biDkZO0k51aumG04CBILqGV2KG97+pqNc kId78sItrozbG4teQLloD2Oj83M8873zfYJOw0FRYGP50NnBcRWJozirxnZV+7gR4bwJ vBv6xz7BYRelyd10++dnEvNRZ/1yenml6XwZ2015ws4Wgpn3xGHeV8OKVc8gmbxBHF0k YWkQ== X-Gm-Message-State: AKGB3mLIzeCmP1iWuZAx6T00xVHnMkw0k+AdyohNoHpIKaUh7mSYoyYF J1LlCs+ioIQJ6oTWrNCVF/PmBmIP36w= X-Google-Smtp-Source: ACJfBosc0MAh0n7R/K14FXHuHbQJlR4JTXYE8BjQ/X7zvxDJ6LSd+1wkRlAlRw4yPWPJcmA5/10c1g== X-Received: by 10.98.153.221 with SMTP id t90mr476687pfk.210.1513619183875; Mon, 18 Dec 2017 09:46:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:48 -0800 Message-Id: <20171218174552.18871-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 19/23] target/arm: Implement SVE Bitwise Shift - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 12 +++++++++++ target/arm/sve_helper.c | 30 ++++++++++++++++++++++++++ target/arm/translate-sve.c | 53 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/sve.def | 21 ++++++++++++++++++ 4 files changed, 116 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index c8eae5eb62..c0e23e7a83 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -362,6 +362,18 @@ DEF_HELPER_FLAGS_4(sve_index_h, TCG_CALL_NO_RWG, void,= ptr, i32, i32, i32) DEF_HELPER_FLAGS_4(sve_index_s, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32) DEF_HELPER_FLAGS_4(sve_index_d, TCG_CALL_NO_RWG, void, ptr, i64, i64, i32) =20 +DEF_HELPER_FLAGS_4(sve_asr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_asr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_asr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_lsr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + DEF_HELPER_FLAGS_5(sve_and_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_bic_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(sve_eor_pred, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index d8684b9457..b6aca18d22 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -669,6 +669,36 @@ DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG) DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG) =20 +/* Three-operand expander, unpredicated, in which the third operand is "wi= de". + */ +#define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; ) { \ + TYPEW mm =3D *(TYPEW *)(vm + i); \ + do { \ + TYPE nn =3D *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) =3D OP(nn, mm); \ + i +=3D sizeof(TYPE); \ + } while (i & 7); \ + } \ +} + +DO_ZZW(sve_asr_zzw_b, int8_t, uint64_t, H1, DO_ASR) +DO_ZZW(sve_lsr_zzw_b, uint8_t, uint64_t, H1, DO_LSR) +DO_ZZW(sve_lsl_zzw_b, uint8_t, uint64_t, H1, DO_LSL) + +DO_ZZW(sve_asr_zzw_h, int16_t, uint64_t, H1_2, DO_ASR) +DO_ZZW(sve_lsr_zzw_h, uint16_t, uint64_t, H1_2, DO_LSR) +DO_ZZW(sve_lsl_zzw_h, uint16_t, uint64_t, H1_2, DO_LSL) + +DO_ZZW(sve_asr_zzw_s, int32_t, uint64_t, H1_4, DO_ASR) +DO_ZZW(sve_lsr_zzw_s, uint32_t, uint64_t, H1_4, DO_LSR) +DO_ZZW(sve_lsl_zzw_s, uint32_t, uint64_t, H1_4, DO_LSL) + +#undef DO_ZZW + #undef DO_CLS_B #undef DO_CLS_H #undef DO_CLZ_B diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 026af7a162..d8e7cc7570 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -657,6 +657,59 @@ void trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t= insn) tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); } =20 +static void do_shift_imm(DisasContext *s, arg_rri_esz *a, + void (*gvec_fn)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, unsigned)) +{ + unsigned vsz =3D size_for_gvec(vec_full_reg_size(s)); + gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), vsz, vsz, a->imm); +} + +void trans_ASR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + do_shift_imm(s, a, tcg_gen_gvec_sari); +} + +void trans_LSR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + do_shift_imm(s, a, tcg_gen_gvec_shri); +} + +void trans_LSL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) +{ + do_shift_imm(s, a, tcg_gen_gvec_shli); +} + +static void do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 = *fn) +{ + unsigned vsz =3D size_for_gvec(vec_full_reg_size(s)); + if (fn =3D=3D NULL) { + unallocated_encoding(s); + return; + } + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vsz, vsz, 0, fn); +} + +#define DO_ZZW(NAME, name) \ +void trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a, uint32_t insn) \ +{ \ + static gen_helper_gvec_3 * const fns[4] =3D { = \ + gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ + gen_helper_sve_##name##_zzw_s, NULL \ + }; \ + do_zzw_ool(s, a, fns[a->esz]); \ +} + +DO_ZZW(ASR, asr) +DO_ZZW(LSR, lsr) +DO_ZZW(LSL, lsl) + +#undef DO_ZZW + static uint64_t pred_esz_mask[4] =3D { 0xffffffffffffffffull, 0x5555555555555555ull, 0x1111111111111111ull, 0x0101010101010101ull diff --git a/target/arm/sve.def b/target/arm/sve.def index 7428ebc5cd..9caed8fc66 100644 --- a/target/arm/sve.def +++ b/target/arm/sve.def @@ -32,6 +32,11 @@ # A combination of tsz:imm3 -- extract (tsz:imm3) - esize %tszimm_shl 22:2 5:5 !function=3Dtszimm_shl =20 +# Similarly for the tszh/tszl pair at 22/16 for zzi +%tszimm16_esz 22:2 16:5 !function=3Dtszimm_esz +%tszimm16_shr 22:2 16:5 !function=3Dtszimm_shr +%tszimm16_shl 22:2 16:5 !function=3Dtszimm_shl + # Either a copy of rd (at bit 0), or a different source # as propagated via the MOVPRFX instruction. %reg_movprfx 0:5 @@ -42,6 +47,7 @@ # instruction patterns. =20 &rri rd rn imm +&rri_esz rd rn imm esz &rrr_esz rd rn rm esz &rpr_esz rd pg rn esz &rprr_esz rd pg rn rm esz @@ -80,6 +86,9 @@ # User must fill in imm. @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 &rpri_esz rn=3D%r= eg_movprfx esz=3D%tszimm_esz =20 +# Similarly without predicate. +@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 &rri_esz esz=3D%tszim= m16_esz + # Basic Load/Store with 9-bit immediate offset @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 &rri imm=3D%imm9_16_10 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 &rri imm=3D%imm9_16_10 @@ -230,6 +239,18 @@ ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_= i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 =20 +### SVE Bitwise Shift - Unpredicated Group + +# SVE bitwise shift by immediate (unpredicated) +ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm imm=3D%ts= zimm16_shr +LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm imm=3D%ts= zimm16_shr +LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm imm=3D%ts= zimm16_shl + +# SVE bitwise shift by wide elements (unpredicated) +ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm_esz # Note si= ze !=3D 3 +LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm_esz # Note si= ze !=3D 3 +LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm_esz # Note si= ze !=3D 3 + ### SVE Predicate Generation Group =20 # SVE initialize predicate (PTRUE, PTRUES) --=20 2.14.3