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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AY0VrenhwgfxRVh8W8VPt2M/vsScMF29p9zDK0Mm/X4=; b=Stx9aPgnYJTueC+9k3sO3WSTQ/X9TarUuGKcrOBi7M/I3tl/CO0AuBbIB6Zkqdz7XH 7NDwoGB8KBMekVxrPVeSysWfv2Lxgz1otjiTCB/shlpKeJ5CcaGJY+EiN2pvzr7yWyL4 /m2T5AzthujkxCHSnlwlpiaAmcUAlJteZelDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AY0VrenhwgfxRVh8W8VPt2M/vsScMF29p9zDK0Mm/X4=; b=djo8jhhxE3suyLETQQVRXC3v2X9gWsQxFvSllAaZrJMiW/ts9CuGjScGu6Qj4O5mXP 6hCa8BuB35jObauxVJzQf5uI10rrjzdBGXfSTtkTSqqNM8qv7gg0srM81iRnU0JOcNBw uVJnRdWtydknyLBt3n3lQv/azbcbAcwht0Zpo97Nth2/zbxREQ9NUjUGsWon370pmizz 0M+8mxtevJjDaUIXqxfS20tT1+G0l+gOStYx6K0/7enSQ5H6EKlgH+umM/9+mQ3xfpo3 Qls9LOXBrsZvxrPwB120Duowbf21eKVg1hA0MZoi0U2GtSBpPQHytNTTOpSiMr6JbXTj 6EYQ== X-Gm-Message-State: AKGB3mIcwkrl9XePXSZ7sJnZIkVyV3kiwNwLthD07AKL/fasodQLCtUl XkVR7XHImN0yY7cnmUApL61P9x2hGVY= X-Google-Smtp-Source: ACJfBosmRluOwXIEIC/JthpDjYMnukld+Hg0tIqmQTwN/xNQd68TldRwlGtRcfvRI6Rhvnu5M+Zt7A== X-Received: by 10.99.45.67 with SMTP id t64mr439169pgt.146.1513619179575; Mon, 18 Dec 2017 09:46:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:45 -0800 Message-Id: <20171218174552.18871-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 16/23] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++ target/arm/sve.def | 13 +++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 83793ab169..7edec8ba96 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -127,6 +127,36 @@ static void do_zzz_genfn(DisasContext *s, arg_rrr_esz = *a, GVecGen3Fn *fn) do_genfn3(s, fn, a->esz, a->rd, a->rn, a->rm); } =20 +void trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_add); +} + +void trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_sub); +} + +void trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_ssadd); +} + +void trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_sssub); +} + +void trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_usadd); +} + +void trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_ussub); +} + void trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) { do_zzz_genfn(s, a, tcg_gen_gvec_and); diff --git a/target/arm/sve.def b/target/arm/sve.def index 3ae871394c..a33fec4f33 100644 --- a/target/arm/sve.def +++ b/target/arm/sve.def @@ -53,6 +53,9 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 +# Three operand +@rd_rn_rm_esz ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz + # Three operand with unused vector element size @rd_rn_rm ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=3D0 =20 @@ -183,6 +186,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg= _rn_rm_esz MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm_esz # MAD MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm_esz # MSB =20 +### SVE Integer Arithmetic - Unpredicated Group + +# SVE integer add/subtract vectors (unpredicated) +ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm_esz +SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm_esz +SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm_esz +UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm_esz +SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm_esz +UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm_esz + ### SVE Logical - Unpredicated Group =20 # SVE bitwise logical operations (unpredicated) --=20 2.14.3