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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id h69sm26553411pfe.107.2017.12.18.09.30.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:30:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FQf6glxcaldRv3XVm7caVixckARRsaMc5X+WPvrI+1Q=; b=Gjd2EjxW4VUsIGGnletlH6KD5vulAJhZ+eHORSEu5usSL7bipoTSvZsbC3uOxtq+H1 sE3MIJl/gx9isPpHjZrC2ID9f31uaWZeki55IMhOK+1N981v3Hrn2WCjp3Oer9AB4Qvr 0mNbzL/QzSI1QvZQGGuQxp/+jkRg5KJn4ahmw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FQf6glxcaldRv3XVm7caVixckARRsaMc5X+WPvrI+1Q=; b=Yofix0W/SAK6qVQHAvqI5p6KURoH6WNo2RpdBtSGYDrOEPC5W4XYbjZbJmoiDO/8nj LY5dpU6RLtn1F4fc2Ehz7kyT+dvoaMQxo2GQxfugku/WYyjEFjxNFCPfbVxqPE09ODW3 FuT388X84/1Laty7IP8FXj2J05RhrMJXDYBoe09Wshi3JQr188ZyIpypldtbTEbn4gAg +zbbldr5tAXz5jJRWqpxvZhF20KZsLnflvfEStrZ7EsHkP93jJe9PFZ4bXecG5cLEO+/ k3TBkBHNrHjFelKiNRHLQi7+vUm/R+0OgL53KNCsn55gHDwKV2Ti55ymAg1DK4h54PaE JMjA== X-Gm-Message-State: AKGB3mLzIJXIY51vRTEOzVA9VxZQtLzP5gCYZXklzPmGA39abHx4ZF/7 DEf+HXjbNTMyrMp49hohs/s/HEK7SKU= X-Google-Smtp-Source: ACJfBosd0sh+0Mr6FOsM0lolWJakbXsu5xWSmAkGtijNh+6IS+U9LoqysVDIHw4txTd6jScawLZk/w== X-Received: by 10.159.255.71 with SMTP id u7mr451945pls.376.1513618232606; Mon, 18 Dec 2017 09:30:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:30:18 -0800 Message-Id: <20171218173022.18418-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218173022.18418-1-richard.henderson@linaro.org> References: <20171218173022.18418-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 5/9] target/arm: Add aa32_vfp_dreg/aa64_vfp_qreg helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Helpers that return a pointer into env->vfp.regs so that we isolate the logic of how to index the regs array for different cpu modes. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 20 +++++++++++++++++++- linux-user/signal.c | 22 ++++++++++++---------- target/arm/arch_dump.c | 8 +++++--- target/arm/helper-a64.c | 13 +++++++------ target/arm/helper.c | 32 ++++++++++++++++++++------------ target/arm/kvm32.c | 4 ++-- target/arm/kvm64.c | 31 ++++++++++--------------------- target/arm/machine.c | 2 +- target/arm/translate-a64.c | 25 ++++++++----------------- target/arm/translate.c | 16 +++++++++------- 10 files changed, 93 insertions(+), 80 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7a705a09a1..e1a8e2880d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -493,7 +493,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64] QEMU_ALIGNED(16); + uint64_t regs[64] QEMU_ALIGNED(16); =20 uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ @@ -2899,4 +2899,22 @@ static inline void *arm_get_el_change_hook_opaque(AR= MCPU *cpu) return cpu->el_change_hook_opaque; } =20 +/** + * aa32_vfp_dreg: + * Return a pointer to the Dn register within env in 32-bit mode. + */ +static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[regno]; +} + +/** + * aa64_vfp_dreg: + * Return a pointer to the Qn register within env in 64-bit mode. + */ +static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[2 * regno]; +} + #endif diff --git a/linux-user/signal.c b/linux-user/signal.c index cf35473671..a9a3f41721 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1487,12 +1487,13 @@ static int target_setup_sigframe(struct target_rt_s= igframe *sf, } =20 for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]= ); + __put_user(q[0], &aux->fpsimd.vregs[i * 2]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr); @@ -1539,12 +1540,13 @@ static int target_restore_sigframe(CPUARMState *env, } =20 for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __get_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]= ); + __get_user(q[0], &aux->fpsimd.vregs[i * 2]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __get_user(fpsr, &aux->fpsimd.fpsr); @@ -1899,7 +1901,7 @@ static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *re= gspace, CPUARMState *env) __put_user(TARGET_VFP_MAGIC, &vfpframe->magic); __put_user(sizeof(*vfpframe), &vfpframe->size); for (i =3D 0; i < 32; i++) { - __put_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]= ); + __put_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __put_user(vfp_get_fpscr(env), &vfpframe->ufp.fpscr); __put_user(env->vfp.xregs[ARM_VFP_FPEXC], &vfpframe->ufp_exc.fpexc); @@ -2206,7 +2208,7 @@ static abi_ulong *restore_sigframe_v2_vfp(CPUARMState= *env, abi_ulong *regspace) return 0; } for (i =3D 0; i < 32; i++) { - __get_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]= ); + __get_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __get_user(fpscr, &vfpframe->ufp.fpscr); vfp_set_fpscr(env, fpscr); diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9e5b2fb31c..26a2c09868 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -99,8 +99,10 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunc= tion f, =20 aarch64_note_init(¬e, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp)); =20 - for (i =3D 0; i < 64; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, float64_val(env->vfp.regs[i= ])); + for (i =3D 0; i < 32; ++i) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + note.vfp.vregs[2*i + 0] =3D cpu_to_dump64(s, q[0]); + note.vfp.vregs[2*i + 1] =3D cpu_to_dump64(s, q[1]); } =20 if (s->dump_info.d_endian =3D=3D ELFDATA2MSB) { @@ -229,7 +231,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f,= CPUARMState *env, arm_note_init(¬e, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp)); =20 for (i =3D 0; i < 32; ++i) { - note.vfp.vregs[i] =3D cpu_to_dump64(s, float64_val(env->vfp.regs[i= ])); + note.vfp.vregs[i] =3D cpu_to_dump64(s, *aa32_vfp_dreg(env, i)); } =20 note.vfp.fpscr =3D cpu_to_dump32(s, vfp_get_fpscr(env)); diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 0bcf02eeb5..750a088803 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -146,20 +146,21 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t = result, uint64_t indices, * the table starts, and numregs the number of registers in the table. * We return the results of the lookups. */ - int shift; + unsigned shift; =20 for (shift =3D 0; shift < 64; shift +=3D 8) { - int index =3D extract64(indices, shift, 8); + unsigned index =3D extract64(indices, shift, 8); if (index < 16 * numregs) { /* Convert index (a byte offset into the virtual table * which is a series of 128-bit vectors concatenated) - * into the correct vfp.regs[] element plus a bit offset + * into the correct register element plus a bit offset * into that element, bearing in mind that the table * can wrap around from V31 to V0. */ - int elt =3D (rn * 2 + (index >> 3)) % 64; - int bitidx =3D (index & 7) * 8; - uint64_t val =3D extract64(env->vfp.regs[elt], bitidx, 8); + unsigned elt =3D (rn * 2 + (index >> 3)) % 64; + unsigned bitidx =3D (index & 7) * 8; + uint64_t *q =3D aa64_vfp_qreg(env, elt >> 1); + uint64_t val =3D extract64(q[elt & 1], bitidx, 8); =20 result =3D deposit64(result, shift, 8, val); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 02d1b57501..7f304111f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -64,15 +64,16 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *b= uf, int reg) /* VFP data registers are always little-endian. */ nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[reg]); + stfq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs +=3D 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + uint64_t *q =3D aa32_vfp_dreg(env, (reg - 32) * 2); + stfq_le_p(buf, q[0]); + stfq_le_p(buf + 8, q[1]); return 16; } } @@ -90,14 +91,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *b= uf, int reg) =20 nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - env->vfp.regs[reg] =3D ldfq_le_p(buf); + *aa32_vfp_dreg(env, reg) =3D ldfq_le_p(buf); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { nregs +=3D 16; if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] =3D ldfq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] =3D ldfq_le_p(buf + 8); + uint64_t *q =3D aa32_vfp_dreg(env, (reg - 32) * 2); + q[0] =3D ldfq_le_p(buf); + q[1] =3D ldfq_le_p(buf + 8); return 16; } } @@ -114,9 +116,12 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, u= int8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - stfq_le_p(buf, env->vfp.regs[reg * 2]); - stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); - return 16; + { + uint64_t *q =3D aa64_vfp_qreg(env, reg); + stfq_le_p(buf, q[0]); + stfq_le_p(buf + 8, q[1]); + return 16; + } case 32: /* FPSR */ stl_p(buf, vfp_get_fpsr(env)); @@ -135,9 +140,12 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, u= int8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - env->vfp.regs[reg * 2] =3D ldfq_le_p(buf); - env->vfp.regs[reg * 2 + 1] =3D ldfq_le_p(buf + 8); - return 16; + { + uint64_t *q =3D aa64_vfp_qreg(env, reg); + q[0] =3D ldfq_le_p(buf); + q[1] =3D ldfq_le_p(buf + 8); + return 16; + } case 32: /* FPSR */ vfp_set_fpsr(env, ldl_p(buf)); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f925a21481..f77c9c494b 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -358,7 +358,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) /* VFP registers */ r.id =3D KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i =3D 0; i < 32; i++) { - r.addr =3D (uintptr_t)(&env->vfp.regs[i]); + r.addr =3D (uintptr_t)aa32_vfp_dreg(env, i); ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { return ret; @@ -445,7 +445,7 @@ int kvm_arch_get_registers(CPUState *cs) /* VFP registers */ r.id =3D KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i =3D 0; i < 32; i++) { - r.addr =3D (uintptr_t)(&env->vfp.regs[i]); + r.addr =3D (uintptr_t)aa32_vfp_dreg(env, i); ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); if (ret) { return ret; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6554c30007..ac728494a4 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -696,21 +696,16 @@ int kvm_arch_put_registers(CPUState *cs, int level) } } =20 - /* Advanced SIMD and FP registers - * We map Qn =3D regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers. */ for (i =3D 0; i < 32; i++) { - int rd =3D i << 1; - uint64_t fp_val[2]; + uint64_t *q =3D aa64_vfp_qreg(env, i); #ifdef HOST_WORDS_BIGENDIAN - fp_val[0] =3D env->vfp.regs[rd + 1]; - fp_val[1] =3D env->vfp.regs[rd]; + uint64_t fp_val[2] =3D { q[1], q[0] }; + reg.addr =3D (uintptr_t)fp_val; #else - fp_val[1] =3D env->vfp.regs[rd + 1]; - fp_val[0] =3D env->vfp.regs[rd]; + reg.addr =3D (uintptr_t)q; #endif reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)(&fp_val); ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; @@ -837,24 +832,18 @@ int kvm_arch_get_registers(CPUState *cs) env->spsr =3D env->banked_spsr[i]; } =20 - /* Advanced SIMD and FP registers - * We map Qn =3D regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers */ for (i =3D 0; i < 32; i++) { - uint64_t fp_val[2]; + uint64_t *q =3D aa64_vfp_qreg(env, i); reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)(&fp_val); + reg.addr =3D (uintptr_t)q; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret) { return ret; } else { - int rd =3D i << 1; #ifdef HOST_WORDS_BIGENDIAN - env->vfp.regs[rd + 1] =3D fp_val[0]; - env->vfp.regs[rd] =3D fp_val[1]; -#else - env->vfp.regs[rd + 1] =3D fp_val[1]; - env->vfp.regs[rd] =3D fp_val[0]; + uint64_t t; + t =3D q[0], q[0] =3D q[1], q[1] =3D t; #endif } } diff --git a/target/arm/machine.c b/target/arm/machine.c index 176274629c..a85c2430d3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -50,7 +50,7 @@ static const VMStateDescription vmstate_vfp =3D { .minimum_version_id =3D 3, .needed =3D vfp_needed, .fields =3D (VMStateField[]) { - VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), + VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64), /* The xregs array is a little awkward because element 1 (FPSCR) * requires a specific accessor, so we have to split it up in * the vmstate: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d246e8f6b5..e17c7269d4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -170,15 +170,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 32; - for (i =3D 0; i < numvfpregs; i +=3D 2) { - uint64_t vlo =3D float64_val(env->vfp.regs[i * 2]); - uint64_t vhi =3D float64_val(env->vfp.regs[(i * 2) + 1]); - cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 " ", - i, vhi, vlo); - vlo =3D float64_val(env->vfp.regs[(i + 1) * 2]); - vhi =3D float64_val(env->vfp.regs[((i + 1) * 2) + 1]); - cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 "\n", - i + 1, vhi, vlo); + for (i =3D 0; i < numvfpregs; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + uint64_t vlo =3D q[0]; + uint64_t vhi =3D q[1]; + cpu_fprintf(f, "q%02d=3D%016" PRIx64 ":%016" PRIx64 "%c", + i, vhi, vlo, (i & 1 ? '\n' : ' ')); } cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); @@ -572,19 +569,13 @@ static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int= regno) */ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) { - int offs =3D offsetof(CPUARMState, vfp.regs[regno * 2]); -#ifdef HOST_WORDS_BIGENDIAN - offs +=3D (8 - (1 << size)); -#endif - assert_fp_access_checked(s); - return offs; + return vec_reg_offset(s, regno, 0, size); } =20 /* Offset of the high half of the 128 bit vector Qn */ static inline int fp_reg_hi_offset(DisasContext *s, int regno) { - assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); + return vec_reg_offset(s, regno, 1, MO_64); } =20 /* Convenience accessors for reading and writing single and double diff --git a/target/arm/translate.c b/target/arm/translate.c index 55afd29b21..a93e26498e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1516,14 +1516,16 @@ static inline void gen_vfp_st(DisasContext *s, int = dp, TCGv_i32 addr) static inline long vfp_reg_offset (int dp, int reg) { - if (dp) + if (dp) { return offsetof(CPUARMState, vfp.regs[reg]); - else if (reg & 1) { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.upper); } else { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.lower); + long ofs =3D offsetof(CPUARMState, vfp.regs[reg >> 1]); + if (reg & 1) { + ofs +=3D offsetof(CPU_DoubleU, l.upper); + } else { + ofs +=3D offsetof(CPU_DoubleU, l.lower); + } + return ofs; } } =20 @@ -12770,7 +12772,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, numvfpregs +=3D 16; } for (i =3D 0; i < numvfpregs; i++) { - uint64_t v =3D float64_val(env->vfp.regs[i]); + uint64_t v =3D *aa32_vfp_dreg(env, i); cpu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx64= "\n", i * 2, (uint32_t)v, i * 2 + 1, (uint32_t)(v >> 32), --=20 2.14.3