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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qnGU08Ok3HOKT9BypgYjb7UsFrnnOqSyAq3bCwaP6gI=; b=eWVA35j2AFFF1UAKOGZCwDfmr7L1IuiSX/a/lgJgUE+gQKy6WEXxWUb/Cucxo38ivr F1at1ASwCqnfuBUPMgNlrBiI+Aa2UpY9JJvIHdoBNmHEzT+w+K9jFjjFvpMueAJISUJ1 QzrLORco8BRX+3olHtQVRVWxJv240qFKANeb0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qnGU08Ok3HOKT9BypgYjb7UsFrnnOqSyAq3bCwaP6gI=; b=HjzZCzvmI0HPX/JnskZE6pKebrG4qW2pKe8LBSRLh6fBdIbczrsgt4E5nO9L1TP5Gn AwpNIIU7Ot48xU5JpPKrdvFOTzru8JRRwMN7i4/y/LVMYHC9J84Neyu7YOJz3C8T+qw+ Tx9WKLbTRAeHZyMxHh8kyOyzoEVs8lNh1XhEZkPZ+CNj7lW375OJkcnu+l3fuROCHGWo xivGTMhgCe9mCJp3QHBGi82AZ1fmh3TQQlew/q7WFf5lB2ogpVmGu11om39PbPblADzg USlOXE3y33e4TuPdpZFVEhgjEbVILaYqO5Ub3mVct29iobiE83NUxk6tsTMKBLIxGNTR 9Hfw== X-Gm-Message-State: AKGB3mJTcV/EAVA10DXWBp8zxtcPmAof+U5DTraZlcWpiRd5kNMhPwcg xusXKVrQ7cvo5jtDoKdI20u1ObnWwMU= X-Google-Smtp-Source: ACJfBovlSrltas3JpBLjgtk2g5b312zYWHYkHjNB6Rxu/FkVWPFVpXg53jJooO61enESJDAe8eUsHQ== X-Received: by 10.159.211.10 with SMTP id bc10mr441386plb.160.1513617879537; Mon, 18 Dec 2017 09:24:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:22 -0800 Message-Id: <20171218172425.18200-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org> References: <20171218172425.18200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v2 08/11] target/arm: Decode aa64 armv8.3 fcadd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 ++++ target/arm/advsimd_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 36 +++++++++++++++++- 3 files changed, 135 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 06ca458614..0f0fc942b0 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -567,6 +567,13 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index d5185165a5..afc2bb1142 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -24,6 +24,18 @@ #include "tcg/tcg-gvec-desc.h" =20 =20 +/* Note that vector data is stored in host-endian 64-bit chunks, + so addressing units smaller than that needs a host-endian fixup. */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q =20 static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) @@ -181,3 +193,84 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void= *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float16 *d =3D vd; + float16 *n =3D vn; + float16 *m =3D vm; + float_status *fpst =3D vfpst; + uint32_t neg_real =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D neg_real ^ 1; + uintptr_t i; + + neg_real <<=3D 15; + neg_imag <<=3D 15; + + for (i =3D 0; i < opr_sz / 2; i +=3D 2) { + float16 e0 =3D n[H2(i)]; + float16 e1 =3D m[H2(i + 1)] ^ neg_imag; + float16 e2 =3D n[H2(i + 1)]; + float16 e3 =3D m[H2(i)] ^ neg_real; + + d[H2(i)] =3D float16_add(e0, e1, fpst); + d[H2(i + 1)] =3D float16_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + uint32_t neg_real =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D neg_real ^ 1; + uintptr_t i; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i)]; + float32 e1 =3D m[H4(i + 1)] ^ neg_imag; + float32 e2 =3D n[H4(i + 1)]; + float32 e3 =3D m[H4(i)] ^ neg_real; + + d[H4(i)] =3D float32_add(e0, e1, fpst); + d[H4(i + 1)] =3D float32_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float64 *d =3D vd; + float64 *n =3D vn; + float64 *m =3D vm; + float_status *fpst =3D vfpst; + uint64_t neg_real =3D extract64(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag =3D neg_real ^ 1; + uintptr_t i; + + neg_real <<=3D 63; + neg_imag <<=3D 63; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + float64 e0 =3D n[i]; + float64 e1 =3D m[i + 1] ^ neg_imag; + float64 e2 =3D n[i + 1]; + float64 e3 =3D m[i] ^ neg_real; + + d[i] =3D float64_add(e0, e1, fpst); + d[i + 1] =3D float64_add(e2, e3, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 85fc7af491..89a0616894 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10696,7 +10696,8 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) int size =3D extract32(insn, 22, 2); bool u =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); - int feature; + int feature, data; + TCGv_ptr fpst; =20 if (!u) { unallocated_encoding(s); @@ -10712,6 +10713,14 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } feature =3D ARM_FEATURE_V8_1_SIMD; break; + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + if (size =3D=3D 0 || (size =3D=3D 3 && !is_q)) { + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_FCMA; + break; default: unallocated_encoding(s); return; @@ -10758,6 +10767,31 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) 0, fn_gvec_ptr); break; =20 + case 0xc: /* FCADD, #90 */ + case 0xe: /* FCADD, #270 */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_fcaddh; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_fcadds; + break; + case 3: + fn_gvec_ptr =3D gen_helper_gvec_fcaddd; + break; + default: + g_assert_not_reached(); + } + data =3D extract32(opcode, 1, 1); + fpst =3D get_fpstatus_ptr(size =3D=3D 1); + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), + data, fn_gvec_ptr); + tcg_temp_free_ptr(fpst); + break; + default: g_assert_not_reached(); } --=20 2.14.3