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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ihqxkNadFMqmm87H014iNHYSjzIdW6NTum55BD40BtQ=; b=fD5ERZbo7rNdc3HjaBilZPCBA2w+YBGug4G7LUS4Oii+vzYCI2uUIzkMKSKXoH4ixR 8HLmDFy1aRcaEp8owvDJku7E0m+0AUJDVMFWczh8FyFmkOX1gKTMAun2JvMR9A7SMEyv 8yXf5HW7G3YRfIvODXK8Bru1gjZ1fs/vFQsfg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ihqxkNadFMqmm87H014iNHYSjzIdW6NTum55BD40BtQ=; b=pw2+RXuo/At/7FuvJ9HdsOhWH/7UVqPHvjYSS+GxBA1Ru045oqbsJsUCYGttp1Z2oX 418fiW32cJa/CPdmu/fnMwbQ5uX63G9OgIM6wooX2n655uPSWDZSrfGz11nWO81rxTVy a2KgHF+XphK+dq7KqyQjwm2JA2D4DLXoZ9SREV+egi/7s5F95VjKoTtXiJ91/bFlt4Pe jaDUrKpwbwZwJpmwMrbQLNj3+b4Z9vKqXUTaKVHPCqgTKHuApUoimIqTDqgOyBX7Fb7W xz9Kwn/XYv0fgqNyW6c1+NJEeXOHZ+QpAwN2DC8RVxqY7Lh7z4vdsubju3gsMwnMh1Md E5dA== X-Gm-Message-State: AKGB3mJatUVE9U49F/o4Btabnmb2VibbLUr7fx2UjfRQULMQb0g1UBUt SjP4i3iCNLr/1drusEo0Z6l9YPcVwBU= X-Google-Smtp-Source: ACJfBotUjFC6wQtsORwHfZsXRANYko8nwPcvqs7Gsx6XfofUw5Kydt01pnG6vNkthck4GlTwxyYtPA== X-Received: by 10.159.252.6 with SMTP id n6mr431673pls.370.1513617877761; Mon, 18 Dec 2017 09:24:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:21 -0800 Message-Id: <20171218172425.18200-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org> References: <20171218172425.18200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 07/11] target/arm: Add ARM_FEATURE_V8_FCMA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Enable it for the "any" CPU used by *-linux-user. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 4 files changed, 4 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e047756b80..7a705a09a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1353,6 +1353,7 @@ enum arm_features { ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 95f550518e..e07184902f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -541,6 +541,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index afe84645af..6cd8ae1459 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1629,6 +1629,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->midr =3D 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 67a01bf7ce..43b42f95fd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -228,6 +228,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ } --=20 2.14.3