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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 03/11] target/arm: Decode aa64 armv8.1 three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 9 +++++ target/arm/advsimd_helper.c | 74 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 83 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 166 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index d103f3d8bf..06ca458614 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -558,6 +558,15 @@ DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) =20 +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index b91d181741..d5185165a5 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -26,6 +26,16 @@ =20 #define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q =20 +static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) +{ + uint64_t *d =3D vd + opr_sz; + uintptr_t i; + + for (i =3D opr_sz; i < max_sz; i +=3D 8) { + *d++ =3D 0; + } +} + /* Signed saturating rounding doubling multiply-accumulate high half, 16-b= it */ static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) @@ -52,6 +62,22 @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint= 32_t src1, return deposit32(e1, 16, 16, e2); } =20 +void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd; + int16_t *n =3D vn; + int16_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 2; ++i) { + d[i] =3D inl_qrdmlah_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-subtract high half, 16-bit= */ static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, int16_t src2, int16_t src3) @@ -78,6 +104,22 @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uin= t32_t src1, return deposit32(e1, 16, 16, e2); } =20 +void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd; + int16_t *n =3D vn; + int16_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 2; ++i) { + d[i] =3D inl_qrdmlsh_s16(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-accumulate high half, 32-b= it */ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) @@ -93,6 +135,22 @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int= 32_t src1, return ret; } =20 +void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int32_t *d =3D vd; + int32_t *n =3D vn; + int32_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 4; ++i) { + d[i] =3D helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + /* Signed saturating rounding doubling multiply-subtract high half, 32-bit= */ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, int32_t src2, int32_t src3) @@ -107,3 +165,19 @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, in= t32_t src1, } return ret; } + +void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, + void *ve, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + int32_t *d =3D vd; + int32_t *n =3D vn; + int32_t *m =3D vm; + CPUARMState *env =3D ve; + uintptr_t i; + + for (i =3D 0; i < opr_sz / 4; ++i) { + d[i] =3D helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0b090fe086..3836e94135 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10678,7 +10678,89 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) /* non-quad vector op */ clear_vec_high(s, rd); } +} + +/* AdvSIMD three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) +{ + void (*fn_gvec_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 4); + int rm =3D extract32(insn, 16, 5); + int size =3D extract32(insn, 22, 2); + bool u =3D extract32(insn, 29, 1); + bool is_q =3D extract32(insn, 30, 1); + int feature; + + if (!u) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + case 0x1: /* SQRDMLSH (vector) */ + if (size !=3D 1 && size !=3D 2) { + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_1_SIMD; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlah_s32; + break; + default: + g_assert_not_reached(); + } + goto do_env; + + case 0x1: /* SQRDMLSH (vector) */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s16; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_qrdmlsh_s32; + break; + default: + g_assert_not_reached(); + } + do_env: + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), cpu_env, + is_q ? 16 : 8, vec_full_reg_size(s), + 0, fn_gvec_ptr); + break; =20 + default: + g_assert_not_reached(); + } } =20 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, @@ -12421,6 +12503,7 @@ static void disas_crypto_two_reg_sha(DisasContext *= s, uint32_t insn) static const AArch64DecodeTable data_proc_simd[] =3D { /* pattern , mask , fn */ { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, + { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra }, { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, --=20 2.14.3