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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mbeIZ3TcaUqejwr/cEv+cMgVUN1N46NmmGoF/XcSOtY=; b=esXy7vVegyHFk9P5fA2e9mnfolvvgvco3GrXJdaIgKa/FQ37KXvtKfFKk9h0kOrHyx F6L3qEYKgDnAsUJ7JDdkr9SsAax0lS+8AKTKBzWW48svRzXD78v1IxAXiFiXwcOeT8+0 V2Oz2J5/Oaw5QPJkd/uFVHsVDUMPg+adUteX8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mbeIZ3TcaUqejwr/cEv+cMgVUN1N46NmmGoF/XcSOtY=; b=sYbOL56900eATY8fPIvtAB8fN0U56RqbdPc3Fme7HbQsmh84zTRqOONe/Etv4dp1wH itjRY+kn1IrbDFasZ9IuzgI/9r4sCI13BR5p8UgqEi4uTqS9JgdfgzSXz1THBBcE/+0W Q0OzC7Hu6HSawzGJaumTYs0Lp4JjYOi51LLsKPQ4p3Kw6I6e+y6Vomkv4Hb64sFnBH+b JJhJ9Y8s7qmJAqmJp0vZMUVU+kkhGxA2bJVAXd2Us7wyYZhUGeBUXJoBzeXfwdx2ITJL bRewLkVeJIUBjXUvc5XI84YinewWUkLLUT0WNy4F/az01ATXLQChfsGLr8x7joZb3nVJ Q/fg== X-Gm-Message-State: AKGB3mKKnNR2B7y12CQAYNWNLpPrmjea5HAC7DL2VLJUpwjzye+WvLyE zl9r+K7NmncfvRKqBBiUACJ8BB7mqr0= X-Google-Smtp-Source: ACJfBot1TFk/jspUed5aNICJEllb9EOqENxgH7fO6DY8RpSH58h4NeN27lS+0wtW+mOvEsAzjWVApA== X-Received: by 10.98.159.16 with SMTP id g16mr420385pfe.53.1513617870110; Mon, 18 Dec 2017 09:24:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:16 -0800 Message-Id: <20171218172425.18200-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org> References: <20171218172425.18200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH v2 02/11] target/arm: Decode aa64 armv8.1 scalar three same extra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++ target/arm/advsimd_helper.c | 109 ++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 2 +- 4 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 target/arm/advsimd_helper.c diff --git a/target/arm/helper.h b/target/arm/helper.h index 2485fc322d..d103f3d8bf 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -366,8 +366,12 @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i= 32, i32) =20 DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) =20 DEF_HELPER_1(neon_narrow_u8, i32, i64) DEF_HELPER_1(neon_narrow_u16, i32, i64) diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c new file mode 100644 index 0000000000..b91d181741 --- /dev/null +++ b/target/arm/advsimd_helper.c @@ -0,0 +1,109 @@ +/* + * ARM AdvSIMD Vector Operations + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" + + +#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q + +/* Signed saturating rounding doubling multiply-accumulate high half, 16-b= it */ +static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Simplify: + * =3D ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 + * =3D ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret =3D (int32_t)src1 * src2; + ret =3D ((int32_t)src3 << 15) + ret + (1 << 14); + ret >>=3D 15; + if (ret !=3D (int16_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 =3D inl_qrdmlah_s16(env, src1, src2, src3); + uint16_t e2 =3D inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 1= 6); + return deposit32(e1, 16, 16, e2); +} + +/* Signed saturating rounding doubling multiply-subtract high half, 16-bit= */ +static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1, + int16_t src2, int16_t src3) +{ + /* Similarly, using subtraction: + * =3D ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16 + * =3D ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15 + */ + int32_t ret =3D (int32_t)src1 * src2; + ret =3D ((int32_t)src3 << 15) - ret + (1 << 14); + ret >>=3D 15; + if (ret !=3D (int16_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? -0x8000 : 0x7fff); + } + return ret; +} + +uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, + uint32_t src2, uint32_t src3) +{ + uint16_t e1 =3D inl_qrdmlsh_s16(env, src1, src2, src3); + uint16_t e2 =3D inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 1= 6); + return deposit32(e1, 16, 16, e2); +} + +/* Signed saturating rounding doubling multiply-accumulate high half, 32-b= it */ +uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlah_s16 above. */ + int64_t ret =3D (int64_t)src1 * src2; + ret =3D ((int64_t)src3 << 31) + ret + (1 << 30); + ret >>=3D 31; + if (ret !=3D (int32_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} + +/* Signed saturating rounding doubling multiply-subtract high half, 32-bit= */ +uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, + int32_t src2, int32_t src3) +{ + /* Simplify similarly to int_qrdmlsh_s16 above. */ + int64_t ret =3D (int64_t)src1 * src2; + ret =3D ((int64_t)src3 << 31) - ret + (1 << 30); + ret >>=3D 31; + if (ret !=3D (int32_t)ret) { + SET_QC(); + ret =3D (ret < 0 ? INT32_MIN : INT32_MAX); + } + return ret; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d8702b10f5..0b090fe086 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7822,6 +7822,95 @@ static void disas_simd_scalar_three_reg_same_fp16(Di= sasContext *s, uint32_t insn tcg_temp_free_ptr(fpst); } =20 +/* AdvSIMD scalar three same extra + * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0 + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+------+---+------+---+--------+---+----+----+ + */ +static void disas_simd_scalar_three_reg_same_extra(DisasContext *s, + uint32_t insn) +{ + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 4); + int rm =3D extract32(insn, 16, 5); + int size =3D extract32(insn, 22, 2); + bool u =3D extract32(insn, 29, 1); + TCGv_i32 ele1, ele2, ele3; + TCGv_i64 res; + int feature; + + if (!u) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0x0: /* SQRDMLAH (vector) */ + case 0x1: /* SQRDMLSH (vector) */ + if (size !=3D 1 && size !=3D 2) { + unallocated_encoding(s); + return; + } + feature =3D ARM_FEATURE_V8_1_SIMD; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + if (!fp_access_check(s)) { + return; + } + + /* Do a single operation on the lowest element in the vector. + * We use the standard Neon helpers and rely on 0 OP 0 =3D=3D 0 + * with no side effects for all these operations. + * OPTME: special-purpose helpers would avoid doing some + * unnecessary work in the helper for the 16 bit cases. + */ + ele1 =3D tcg_temp_new_i32(); + ele2 =3D tcg_temp_new_i32(); + ele3 =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, ele1, rn, 0, size); + read_vec_element_i32(s, ele2, rm, 0, size); + read_vec_element_i32(s, ele3, rd, 0, size); + + switch (opcode) { + case 0x0: /* SQRDMLAH */ + if (size =3D=3D 1) { + gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + case 0x1: /* SQRDMLSH */ + if (size =3D=3D 1) { + gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); + } else { + gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); + } + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_i32(ele1); + tcg_temp_free_i32(ele2); + + res =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(res, ele3); + tcg_temp_free_i32(ele3); + + write_fp_dreg(s, rd, res); + tcg_temp_free_i64(res); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -12344,6 +12433,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, { 0x2e000000, 0xbf208400, disas_simd_ext }, { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, + { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra }, { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 847fb52ee0..c2d32988f9 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64)= )) +=3D kvm32.o obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) +=3D kvm64.o obj-$(call lnot,$(CONFIG_KVM)) +=3D kvm-stub.o obj-y +=3D translate.o op_helper.o helper.o cpu.o -obj-y +=3D neon_helper.o iwmmxt_helper.o +obj-y +=3D neon_helper.o iwmmxt_helper.o advsimd_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-y +=3D crypto_helper.o --=20 2.14.3