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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hQz2mr3ZIxdEcu/gt27H94bv5BFl3Ifu10zuNk+r8Z0=; b=LvfLkzDaW61FQZ2MRqAWnj6bawkTM4xyf1pHRclH3oFl0hOrnKLT74bTaroEzBakSW 5kNpalLoffuYoPReLD4Lcl4yaoQZvejnFIwLJ/A4SLdkuG+YgaYmi1tCw8ALGC73WQai 2Wv3UUl87VHFdXr1BWkBfjutXBl0HN1Pvq36c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hQz2mr3ZIxdEcu/gt27H94bv5BFl3Ifu10zuNk+r8Z0=; b=nv3HYYTpn2gCOD8gt4uq6HidPDzfVov/V7oqKBOhlwKBl3CqezDfRQFjiNWqiB44HL Q9beRWeBEMuYAtjQnDic93xCLTGJ63SFo0vIqT74XO+B3r01vm0uemVsJpbOXCMH/mG4 NiZJLi+GJJvPbR9k11vf8yO58cNF2JoJMZtyjBzvG17tk9KPWxGfgUXvnGFm+Wl4nhQ0 1+DULCrPyw4C5UZB+ToSQS57MgAnOWHnNZWN1f1oy3/RZcWHRUXMzsFrJkYKxQs6Piml kTIfMT+4kXhqN4tucR1C5ofNAJDRF3UsDK8bUz24NdhY7+3LH1vblsNGOTH7iiDW2SXI nZzw== X-Gm-Message-State: AKGB3mKkh3Zd99pBjMAozyt8+yFW63QOb+u/sbTtGJXOs12tjzp9hR+z sxineLS//U395JIgf/YFY4mOWASIfZo= X-Google-Smtp-Source: ACJfBovGChYO8e4/PbipKncee4Vltg41Dfyx7Al1tXf+Y1SJr9Xal0T69fJQe33+ra1mLeUFg1TyfQ== X-Received: by 10.98.134.65 with SMTP id x62mr413468pfd.81.1513617868578; Mon, 18 Dec 2017 09:24:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:15 -0800 Message-Id: <20171218172425.18200-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org> References: <20171218172425.18200-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 01/11] target/arm: Add ARM_FEATURE_V8_1_SIMD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Enable it for the "any" CPU used by *-linux-user. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + linux-user/elfload.c | 9 +++++++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + 4 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 715ec6a476..e047756b80 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1351,6 +1351,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c3..95f550518e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,14 @@ enum { ARM_HWCAP_A64_SHA1 =3D 1 << 5, ARM_HWCAP_A64_SHA2 =3D 1 << 6, ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +540,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); #undef GET_FEATURE =20 return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7f7a3d1e32..afe84645af 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1628,6 +1628,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); cpu->midr =3D 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0dc4debd9c..67a01bf7ce 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ --=20 2.14.3