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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id m10sm9260469pgs.4.2017.12.18.09.24.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:24:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iQ5LZPZSGs0K79ksja0IDxF/0z6h8Y8IG7iuFV2P9oE=; b=bUgBGTLo94QeFWhh1hKBIXzASpcVfcPy0+IUfoA8V0E0MK2fDQF2uy7SC+IbxTOs+x HmM1MpLXmC4LvEI+yKYQt4IhLXW37rQHLNl//VJzlNW2f7fgjuZEHCBhfjRStWQgSBxY eajdJCkXW8z0qQa/ntUdReEnH1MA0BVUhqQI8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iQ5LZPZSGs0K79ksja0IDxF/0z6h8Y8IG7iuFV2P9oE=; b=KyGoPEkIwGQF8lb6CPuHihHLZYtK9bPsfiXyppmdStdy+H+2k6shUPZpMf9K/t2o5n cZBVpmyfx+zJskRvRm+fGOrkgoSSYj2PuGfrxeO+AL1hyIgD/F2cMv4O5cYkPJCq7KRK TyEav6OiNDVX4HYntztWUQhohhZo+TtzkNEYTPbQPfQl1DEJFxcGY2FOsIKm1h44PSyC dNHyeLcbjz1Wu5mrh+22E2Iii63ZrsJFQgr4BCNpBbHHxWETvBam+4Domq2LHiqdh78y 6a/Ig/O/1fcuL2LD9vS6+uSLnSszHxwwH4Gv+wJtT28ZOICQI2vs71VoAJlKxlCoc6LY pgew== X-Gm-Message-State: AKGB3mLzH2omOyAEb5aVLc63Yxke1H39EX6rDgx80tw9CB0qtDJ2DoNl atVLY/HPSKrwR2B3OXpI/mUI+vfL4cQ= X-Google-Smtp-Source: ACJfBotp8sQh08PBT9iE1MqlGFMhfcNmUcEOMB4T9606FerZWbpJI6SYrF7gL8TeIcQ2ZnFsDq2DQQ== X-Received: by 10.84.130.41 with SMTP id 38mr421802plc.131.1513617880925; Mon, 18 Dec 2017 09:24:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:24:23 -0800 Message-Id: <20171218172425.18200-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org> References: <20171218172425.18200-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3 fcmla X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 11 ++++ target/arm/advsimd_helper.c | 144 ++++++++++++++++++++++++++++++++++++++++= ++ target/arm/translate-a64.c | 149 ++++++++++++++++++++++++++++++++--------= ---- 3 files changed, 265 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 0f0fc942b0..5b6333347d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -574,6 +574,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target/arm/advsimd_helper.c b/target/arm/advsimd_helper.c index afc2bb1142..6a2a53e111 100644 --- a/target/arm/advsimd_helper.c +++ b/target/arm/advsimd_helper.c @@ -274,3 +274,147 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float16 *d =3D vd; + float16 *n =3D vn; + float16 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + + neg_real <<=3D 15; + neg_imag <<=3D 15; + + for (i =3D 0; i < opr_sz / 2; i +=3D 2) { + float16 e0 =3D n[H2(i + flip)]; + float16 e1 =3D m[H2(i + flip)] ^ neg_real; + float16 e2 =3D e0; + float16 e3 =3D m[H2(i + 1 - flip)] ^ neg_imag; + + d[H2(i)] =3D float16_muladd(e0, e1, d[H2(i)], 0, fpst); + d[H2(i + 1)] =3D float16_muladd(e2, e3, d[H2(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float16 *d =3D vd; + float16 *n =3D vn; + float16 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + float16 e1 =3D m[H2(flip)]; + float16 e3 =3D m[H2(1 - flip)]; + + neg_real <<=3D 15; + neg_imag <<=3D 15; + e1 ^=3D neg_real; + e3 ^=3D neg_imag; + + for (i =3D 0; i < opr_sz / 2; i +=3D 2) { + float16 e0 =3D n[H2(i + flip)]; + float16 e2 =3D e0; + + d[H2(i)] =3D float16_muladd(e0, e1, d[H2(i)], 0, fpst); + d[H2(i + 1)] =3D float16_muladd(e2, e3, d[H2(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i + flip)]; + float32 e1 =3D m[H4(i + flip)] ^ neg_real; + float32 e2 =3D e0; + float32 e3 =3D m[H4(i + 1 - flip)] ^ neg_imag; + + d[H4(i)] =3D float32_muladd(e0, e1, d[H4(i)], 0, fpst); + d[H4(i + 1)] =3D float32_muladd(e2, e3, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float32 *d =3D vd; + float32 *n =3D vn; + float32 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint32_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint32_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + float32 e1 =3D m[H4(flip)]; + float32 e3 =3D m[H4(1 - flip)]; + + neg_real <<=3D 31; + neg_imag <<=3D 31; + e1 ^=3D neg_real; + e3 ^=3D neg_imag; + + for (i =3D 0; i < opr_sz / 4; i +=3D 2) { + float32 e0 =3D n[H4(i + flip)]; + float32 e2 =3D e0; + + d[H4(i)] =3D float32_muladd(e0, e1, d[H4(i)], 0, fpst); + d[H4(i + 1)] =3D float32_muladd(e2, e3, d[H4(i + 1)], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, + void *vfpst, uint32_t desc) +{ + uintptr_t opr_sz =3D simd_oprsz(desc); + float64 *d =3D vd; + float64 *n =3D vn; + float64 *m =3D vm; + float_status *fpst =3D vfpst; + intptr_t flip =3D extract32(desc, SIMD_DATA_SHIFT, 1); + uint64_t neg_imag =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + uint64_t neg_real =3D flip ^ neg_imag; + uintptr_t i; + + neg_real <<=3D 63; + neg_imag <<=3D 63; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + float64 e0 =3D n[i + flip]; + float64 e1 =3D m[i + flip] ^ neg_real; + float64 e2 =3D e0; + float64 e3 =3D m[i + 1 - flip] ^ neg_imag; + + d[i] =3D float64_muladd(e0, e1, d[i], 0, fpst); + d[i + 1] =3D float64_muladd(e2, e3, d[i + 1], 0, fpst); + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 89a0616894..79fede35c1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10713,6 +10713,10 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) } feature =3D ARM_FEATURE_V8_1_SIMD; break; + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ if (size =3D=3D 0 || (size =3D=3D 3 && !is_q)) { @@ -10767,6 +10771,26 @@ static void disas_simd_three_reg_same_extra(DisasC= ontext *s, uint32_t insn) 0, fn_gvec_ptr); break; =20 + case 0x8: /* FCMLA, #0 */ + case 0x9: /* FCMLA, #90 */ + case 0xa: /* FCMLA, #180 */ + case 0xb: /* FCMLA, #270 */ + switch (size) { + case 1: + fn_gvec_ptr =3D gen_helper_gvec_fcmlah; + break; + case 2: + fn_gvec_ptr =3D gen_helper_gvec_fcmlas; + break; + case 3: + fn_gvec_ptr =3D gen_helper_gvec_fcmlad; + break; + default: + g_assert_not_reached(); + } + data =3D extract32(opcode, 0, 2); + goto do_fpst; + case 0xc: /* FCADD, #90 */ case 0xe: /* FCADD, #270 */ switch (size) { @@ -10783,6 +10807,7 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) g_assert_not_reached(); } data =3D extract32(opcode, 1, 1); + do_fpst: fpst =3D get_fpstatus_ptr(size =3D=3D 1); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), @@ -11864,80 +11889,80 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); bool is_long =3D false; - bool is_fp =3D false; + int is_fp =3D 0; + bool is_fp16 =3D false; int index; TCGv_ptr fpst; =20 - switch (opcode) { - case 0x0: /* MLA */ - case 0x4: /* MLS */ - if (!u || is_scalar) { + switch (16 * u + opcode) { + case 0x00: /* MLA */ + case 0x04: /* MLS */ + case 0x08: /* MUL */ + if (is_scalar) { unallocated_encoding(s); return; } break; - case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ - case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ - case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ + case 0x02: /* SMLAL, SMLAL2 */ + case 0x12: /* UMLAL, UMLAL2 */ + case 0x06: /* SMLSL, SMLSL2 */ + case 0x16: /* UMLSL, UMLSL2 */ + case 0x0a: /* SMULL, SMULL2 */ + case 0x1a: /* UMULL, UMULL2 */ if (is_scalar) { unallocated_encoding(s); return; } is_long =3D true; break; - case 0x3: /* SQDMLAL, SQDMLAL2 */ - case 0x7: /* SQDMLSL, SQDMLSL2 */ - case 0xb: /* SQDMULL, SQDMULL2 */ + case 0x03: /* SQDMLAL, SQDMLAL2 */ + case 0x07: /* SQDMLSL, SQDMLSL2 */ + case 0x0b: /* SQDMULL, SQDMULL2 */ is_long =3D true; - /* fall through */ - case 0xc: /* SQDMULH */ - if (u) { - unallocated_encoding(s); - return; - } break; - case 0xd: /* SQRDMULH / SQRDMLAH */ - if (u && !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { - unallocated_encoding(s); - return; - } + case 0x0c: /* SQDMULH */ + case 0x0d: /* SQRDMULH */ break; - case 0xf: /* SQRDMLSH */ - if (!u || !arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { + case 0x1d: /* SQRDMLAH */ + case 0x1f: /* SQRDMLSH */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) { unallocated_encoding(s); return; } break; - case 0x8: /* MUL */ - if (u || is_scalar) { + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { unallocated_encoding(s); return; } + is_fp =3D 2; break; - case 0x1: /* FMLA */ - case 0x5: /* FMLS */ - if (u) { - unallocated_encoding(s); - return; - } - /* fall through */ - case 0x9: /* FMUL, FMULX */ - if (size =3D=3D 1 || (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V= 8_FP16))) { + case 0x01: /* FMLA */ + case 0x05: /* FMLS */ + case 0x09: /* FMUL */ + case 0x19: /* FMULX */ + if (size =3D=3D 1 + || (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { unallocated_encoding(s); return; } - is_fp =3D true; + is_fp =3D 1; break; default: unallocated_encoding(s); return; } =20 - if (is_fp) { + switch (is_fp) { + case 1: /* normal fp */ /* convert insn encoded size to TCGMemOp size */ switch (size) { case 0: /* half-precision */ size =3D MO_16; + is_fp16 =3D true; index =3D h << 2 | l << 1 | m; break; case 2: /* single precision */ @@ -11958,7 +11983,36 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) g_assert_not_reached(); break; } - } else { + break; + + case 2: /* complex fp */ + switch (size) { + case 1: + size =3D MO_32; + is_fp16 =3D true; + if (h && !is_q) { + unallocated_encoding(s); + return; + } + index =3D h << 1 | l; + rm |=3D (m << 4); + break; + case 2: + size =3D MO_64; + if (l || !is_q) { + unallocated_encoding(s); + return; + } + index =3D h; + rm |=3D (m << 4); + break; + default: + unallocated_encoding(s); + return; + } + break; + + default: /* integer */ switch (size) { case 1: index =3D h << 2 | l << 1 | m; @@ -11978,11 +12032,28 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) } =20 if (is_fp) { - fpst =3D get_fpstatus_ptr(false); + fpst =3D get_fpstatus_ptr(is_fp16); } else { fpst =3D NULL; } =20 + switch (16 * u + opcode) { + case 0x11: /* FCMLA #0 */ + case 0x13: /* FCMLA #90 */ + case 0x15: /* FCMLA #180 */ + case 0x17: /* FCMLA #270 */ + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_reg_offset(s, rm, index, size), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), + extract32(insn, 13, 2), /* rot */ + size =3D=3D MO_64 + ? gen_helper_gvec_fcmlas_idx + : gen_helper_gvec_fcmlah_idx); + tcg_temp_free_ptr(fpst); + return; + } + if (size =3D=3D 3) { TCGv_i64 tcg_idx =3D tcg_temp_new_i64(); int pass; --=20 2.14.3