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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH 3/4] hw/pci-host/xilinx: QOM'ify the AXI-PCIe host bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/xilinx-pcie.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 7659253090..756db39fd5 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -267,24 +267,23 @@ static void xilinx_pcie_root_config_write(PCIDevice *= d, uint32_t address, } } =20 -static int xilinx_pcie_root_init(PCIDevice *dev) +static void xilinx_pcie_root_realize(PCIDevice *pci, Error **errp) { - BusState *bus =3D qdev_get_parent_bus(DEVICE(dev)); + DeviceState *dev =3D DEVICE(pci); + BusState *bus =3D qdev_get_parent_bus(dev); XilinxPCIEHost *s =3D XILINX_PCIE_HOST(bus->parent); =20 - pci_set_word(dev->config + PCI_COMMAND, + pci_set_word(pci->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_set_word(dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16); - pci_set_word(dev->config + PCI_MEMORY_LIMIT, + pci_set_word(pci->config + PCI_MEMORY_BASE, s->mmio_base >> 16); + pci_set_word(pci->config + PCI_MEMORY_LIMIT, ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0); =20 - pci_bridge_initfn(dev, TYPE_PCI_BUS); + pci_bridge_initfn(pci, TYPE_PCI_BUS); =20 - if (pcie_endpoint_cap_v1_init(dev, 0x80) < 0) { + if (pcie_endpoint_cap_v1_init(pci, 0x80) < 0) { hw_error("Failed to initialize PCIe capability"); } - - return 0; } =20 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) @@ -300,7 +299,7 @@ static void xilinx_pcie_root_class_init(ObjectClass *kl= ass, void *data) k->class_id =3D PCI_CLASS_BRIDGE_HOST; k->is_express =3D true; k->is_bridge =3D true; - k->init =3D xilinx_pcie_root_init; + k->realize =3D xilinx_pcie_root_realize; k->exit =3D pci_bridge_exitfn; dc->reset =3D pci_bridge_reset; k->config_read =3D xilinx_pcie_root_config_read; --=20 2.15.1