From nobody Sat Feb 7 09:42:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513415420834390.21530516294536; Sat, 16 Dec 2017 01:10:20 -0800 (PST) Received: from localhost ([::1]:49884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQ8Tv-0001kX-17 for importer@patchew.org; Sat, 16 Dec 2017 04:10:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQ8N3-0004jU-Bf for qemu-devel@nongnu.org; Sat, 16 Dec 2017 04:03:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eQ8Mz-00024E-GX for qemu-devel@nongnu.org; Sat, 16 Dec 2017 04:03:01 -0500 Received: from iserv.reactos.org ([2a01:4f8:221:4c5::3]:58815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eQ8Mz-0001yo-AE for qemu-devel@nongnu.org; Sat, 16 Dec 2017 04:02:57 -0500 Received: from [2a01:e34:ee6b:9c80:6267:20ff:fe65:a488] (helo=localhost.localdomain) by iserv.reactos.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1eQ8Ml-0001v2-Pi; Sat, 16 Dec 2017 09:02:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=reactos.org; s=25047; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=AoyjMdDDBbyTv/52IB1ODZzrLNtf/SJpuVK79P4u8Ws=; b=Xr/xIo/fiYMW4h7NDo6dyyhihIEPp5gSCQ4lp/7jS0oLqDmBqj/HQb0LednhHiGD9eY07yNoE/aiGX/8Ig2IaRPVw/FPqChmFizTnxg1Fu5D7Cp3KhSFQR3iSnte+DbgYK0o1k1L/ec9kOtawgwBh0yJGJg/S/sfJkknyz2vi78=; From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: Aurelien Jarno , Yongbok Kim , "Michael S . Tsirkin" , Paolo Bonzini , qemu-devel@nongnu.org Date: Sat, 16 Dec 2017 10:02:19 +0100 Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171216090228.28505-1-hpoussin@reactos.org> References: <20171216090228.28505-1-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a01:4f8:221:4c5::3 Subject: [Qemu-devel] [PATCH 06/15] piix4: add Reset Control Register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Signed-off-by: Herv=C3=A9 Poussineau --- hw/isa/piix4.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4f476dc7e6..7c83e7c23d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2016 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -33,6 +34,10 @@ PCIDevice *piix4_dev; =20 typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; =20 #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,6 +92,30 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s =3D opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr =3D val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s =3D opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops =3D { + .read =3D piix4_rcr_read, + .write =3D piix4_rcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + static void piix4_realize(PCIDevice *pci, Error **errp) { DeviceState *dev =3D DEVICE(pci); @@ -96,6 +125,12 @@ static void piix4_realize(PCIDevice *pci, Error **errp) pci_address_space_io(pci), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci), 0xcf9, + &s->rcr_mem, 1); + piix4_dev =3D pci; qemu_register_reset(piix4_reset, s); } --=20 2.11.0