From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151335805741019.918023539790738; Fri, 15 Dec 2017 09:14:17 -0800 (PST) Received: from localhost ([::1]:47809 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtYe-0006OQ-D2 for importer@patchew.org; Fri, 15 Dec 2017 12:14:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtSX-0001RY-I4 for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePtSV-0002s3-RE for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:41 -0500 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:45461) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ePtSV-0002r4-L0 for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:39 -0500 Received: by mail-it0-x243.google.com with SMTP id z6so21035117iti.4 for ; Fri, 15 Dec 2017 09:07:39 -0800 (PST) Received: from cloudburst.twiddle.net (141-126-166-226.dhcp.chtrptr.net. [141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=khE8rSygkJxKJIlL4o6HtdlZEHgkFCJk+nQSZzTHpP0=; b=OZlzhpDU3X0/tI5IGpOBbzga2tVVOShE7zrGvv4fW30fI7ZKhCCzHjmB7Kd7proi6r tjPVJFuIiSKUFOciJpAIvbNGQqStK6XO5KevFjKC52zSaZs8vSndjnpJR6uu5G3LuhM1 tI8bCBb1Ff4pnlq6QMwhEOvQQN786XRZUA45g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=khE8rSygkJxKJIlL4o6HtdlZEHgkFCJk+nQSZzTHpP0=; b=bx0nmhMXrXhszNPRGRrdtQ2o2r1J0Nf9fM87ochGOJWb2d/fk7FMCtXZU1sh538EKu vGu0GACw2V/j1c05WGa6N7tDEkkTBRRMO3++fDDZXWBeW8C6d28njxWqVkLc/vHkK6Fq UOeH/k1Luuio8ohpN8vhD3dksY6bJtKxZ/0lv/ehBbGpyfTF9P2wUSoPTIVxpIGaoduk jaM6+wepxl2n8FjhoKF7unFq3Qie+swVfCuwI3VInY4EllIdG2o6cC+watzcZp7wEAdJ 2kztM3l6iw6OPwRcOTdu+jD3vO2fw2pvY/4cq3yCKtf+BL0jNLPjiJYJ3xCMWKEwMAqI sDgA== X-Gm-Message-State: AKGB3mKGk9/yxeQsVNVctoP0TWGdpTqlL1yW6f4GR3MMBH+YCgXVX+iY dH96/zFe/Sr8yqFvwxLL0fmYxoPrerc= X-Google-Smtp-Source: ACJfBovrsMJOeU8LTNwdcL28HHbZupMofaFU5ngp5F5RFwsdAGxDMMAh8z2yBuGPI/R+IEzs7zOGEg== X-Received: by 10.36.39.9 with SMTP id g9mr8607296ita.91.1513357658616; Fri, 15 Dec 2017 09:07:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:26 -0600 Message-Id: <20171215170732.31125-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 1/7] target/*helper: don't check retaddr before calling cpu_restore_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Benn=C3=A9e [rth: Fixed up comment indentation. Added second hunk to script to combine cpu_restore_state and cpu_loop_exit.] Signed-off-by: Richard Henderson --- target/alpha/mem_helper.c | 13 +++---------- target/arm/op_helper.c | 18 ++++++------------ target/i386/svm_helper.c | 4 +--- target/lm32/op_helper.c | 7 ++----- target/m68k/op_helper.c | 7 ++----- target/microblaze/op_helper.c | 7 ++----- target/moxie/helper.c | 4 +--- target/nios2/mmu.c | 7 ++----- target/openrisc/mmu_helper.c | 6 +----- target/tricore/op_helper.c | 13 +++---------- target/unicore32/op_helper.c | 7 ++----- scripts/coccinelle/cpu_restore_state.cocci | 19 +++++++++++++++++++ 12 files changed, 44 insertions(+), 68 deletions(-) create mode 100644 scripts/coccinelle/cpu_restore_state.cocci diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 3c06baa93a..430eea470b 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -34,9 +34,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr ad= dr, uint64_t pc; uint32_t insn; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -58,9 +56,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; @@ -80,11 +76,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D alpha_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret !=3D 0)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } /* Exception index and error code are already set */ - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, retaddr); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c2bb4f3a43..b36206343d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -182,10 +182,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, if (unlikely(ret)) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } @@ -199,10 +197,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 fi.type =3D ARMFault_Alignment; deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); @@ -221,10 +217,8 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; =20 - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 /* The EA bit in syndromes and fault status registers is an * IMPDEF classification of external aborts. ARM implementations diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index f479239875..303106981c 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -584,9 +584,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, { CPUState *cs =3D CPU(x86_env_get_cpu(env)); =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 2177c8ad12..30f670eee8 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -151,11 +151,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, =20 ret =3D lm32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 63089511cb..78bfb9f0cc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } =20 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1e07e21c1c..4cf51568df 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -40,11 +40,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 330299f5a7..2ecee89f11 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -36,9 +36,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 ret =3D moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index fe9298af50..0cd8647510 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -42,11 +42,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } =20 diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a44d0aa51a..a3e182c42d 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -33,12 +33,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); =20 if (ret) { - if (retaddr) { - /* now we have a real cpu fault. */ - cpu_restore_state(cs, retaddr); - } /* Raise Exception. */ - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 7af202c8c0..40ed229486 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,9 +31,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint3= 2_t class, int tin, { CPUState *cs =3D CPU(tricore_env_get_cpu(env)); /* in case we come from a helper-call we need to restore the PC */ - if (pc) { - cpu_restore_state(cs, pc); - } + cpu_restore_state(cs, pc); =20 /* Tin is loaded into d[15] */ env->gpr_d[15] =3D tin; @@ -2804,13 +2802,8 @@ static inline void QEMU_NORETURN do_raise_exception_= err(CPUTriCoreState *env, CPUState *cs =3D CPU(tricore_env_get_cpu(env)); cs->exception_index =3D exception; env->error_code =3D error_code; - - if (pc) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, pc); - } - - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, pc); } =20 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 0872c29faa..8788642a7f 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -251,11 +251,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, =20 ret =3D uc32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } - cpu_loop_exit(cs); + /* now we have a real cpu fault */ + cpu_loop_exit_restore(cs, retaddr); } } #endif diff --git a/scripts/coccinelle/cpu_restore_state.cocci b/scripts/coccinell= e/cpu_restore_state.cocci new file mode 100644 index 0000000000..61bc749d14 --- /dev/null +++ b/scripts/coccinelle/cpu_restore_state.cocci @@ -0,0 +1,19 @@ +// Remove unneeded tests before calling cpu_restore_state +// +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file ./scripts/coccinelle/cpu_restore_state.cocci \ +// --keep-comments --in-place --use-gitgrep --dir target +@@ +expression A; +expression C; +@@ +-if (A) { + cpu_restore_state(C, A); +-} +@@ +expression A; +expression C; +@@ +- cpu_restore_state(C, A); +- cpu_loop_exit(C); ++ cpu_loop_exit_restore(C, A); --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=duqz0zTygyg/WZ14UBKd2/c6PKeoS+BjyHmQuSaknYk=; b=EutE1jq0VyBUcIJ/vJiSFVyTZr8DDYZxmU3mO37+k1EHRsdtwFHYHutwnbRtu2FyyZ PjA45A82kaW4ZYmrg8qIZQxS8bQ/DIyBxXKy2UVBJQNUefh+z3NJsCC73ypkEzrcDfM6 wXA32KkTzwQoOMkIZnCzZf4Dmuzcgjx12SJVE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=duqz0zTygyg/WZ14UBKd2/c6PKeoS+BjyHmQuSaknYk=; b=AFXwAVZZKSLKXMpNr9Gy4tjHU6kTz06b9FxyG94pxwLJ/HE3rO/jsAEuBJm1v5ONSY x7UZtoSRIhKNNiVHQ5IubnIB3QpZyBMZRPmB1kk/SfEht3glMJriXqTlEhNld7UR4+ig OtX4ES+jpj+1t//aFfgVmp1A0taklag2+jVps+jXINRecXdfb9ceonvRhcuykh6sxpVq 1CAmsn/Y0Vu3p0dfzKubmlT2+kFuT2oH1y9AullIh2DPPpcbthTi3k4+P+XOLQuAqIb5 Mt4e2x9sCSw+dXlRP0rrZo3YmL97sM8q2ROJk1nUFdziRu159C08WQe267BJ5i0nJeBf MO9w== X-Gm-Message-State: AKGB3mJvyqqo8k4/1QBFkzhBXcP9NmPb74sUccTKrtEp9Ce+oJn0IIHK KKVdiMDQ8e8Hkvy5rJBScjSxxaXlRas= X-Google-Smtp-Source: ACJfBotVsGnn4+5fGbXM286gl6T1WGsZGSGz/iIwTsTMCiBAJCnac0VGMZnBtz07r+4c9VGELGjmJQ== X-Received: by 10.36.135.5 with SMTP id f5mr9675542ite.85.1513357660046; Fri, 15 Dec 2017 09:07:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:27 -0600 Message-Id: <20171215170732.31125-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 2/7] target/moxie: Fix tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We should not exit unless moxie_cpu_handle_mmu_fault has failed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/moxie/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 2ecee89f11..6890ffd71c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -36,9 +36,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 ret =3D moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - cpu_restore_state(cs, retaddr); + cpu_loop_exit_restore(cs, retaddr); } - cpu_loop_exit(cs); } =20 void helper_raise_exception(CPUMoxieState *env, int ex) --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513357795754759.1521585658159; Fri, 15 Dec 2017 09:09:55 -0800 (PST) Received: from localhost ([::1]:47783 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtUW-0002jz-Ct for importer@patchew.org; Fri, 15 Dec 2017 12:09:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtSc-0001Uq-IZ for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePtSZ-0002vb-Bo for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:46 -0500 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:41969) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ePtSZ-0002v9-2M for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:43 -0500 Received: by mail-it0-x243.google.com with SMTP id x28so21179995ita.0 for ; Fri, 15 Dec 2017 09:07:43 -0800 (PST) Received: from cloudburst.twiddle.net (141-126-166-226.dhcp.chtrptr.net. [141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=KySiI8yaRzLDLGE754W7xusXkte0cXVk7VKZnf0ptAg=; b=TTJsfll9uZXHhIfR0ovN79XQoVmzBbXUk4G1n7Z4lNfwG1eRt6xBrxpjqgr4tQ5KnO 7XODIitGkYzSqvMyVvg4UcQsP9Ez3h6jQijHZd8QEcFlM5cAC/Ll4+qZZsijsyFb9ABh flNYoVn3Y5uTVetzPqSoxnDDJqZReF57n49U0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=KySiI8yaRzLDLGE754W7xusXkte0cXVk7VKZnf0ptAg=; b=AlQ9/F6XSPydupxXV1i60VjmC/KO7aJ1YaH19UXtNGh9vQUErPPBjpoUCLeBCEkEU2 eRzO+uYZlIoi+8PZBp/tiyiggNzZzOwZPtM5D1M7PMZ1NJ2A5FYQjmbfVBEN9DUdHysZ qm6/NOgyJRZPwYXf39FlTglueF+McGm3jWeMHCAVB2m1R6EVBI4W2vzZqLJrVayQf23G NeSUwaUcJ6JvJKYGbVSV43AMJBwoCarPu1uPpMDEC/qp7JW83C5+LISGE0kifA1hQkfs W69jLF5KiRioSqmde3iSDmW1bZTqd0wg7XVb6C2ZRHbJ8qJSChXE79XLvY45nsXDicjx O4eA== X-Gm-Message-State: AKGB3mIL1fnFvU1c/xn0l17fW4OiRY66An5o8QJyP7FsQQhi4nheMYMK QO0CE5U4J7wp8l7X32sip05H2klk6tk= X-Google-Smtp-Source: ACJfBouVhgh6YkTSPqe2KqA5Sc4OcAtjhFN4Ph8wLmp/ZFep5EXTmVk2ik7rUjBynmza1GtGWC2vCw== X-Received: by 10.36.117.87 with SMTP id y84mr8508916itc.124.1513357661851; Fri, 15 Dec 2017 09:07:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:28 -0600 Message-Id: <20171215170732.31125-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 3/7] tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These are now trivial sets and tests against NULL. Unwrap. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg-op.h | 4 --- tcg/tcg.h | 9 ------- target/alpha/translate.c | 22 ++++++++-------- target/arm/translate-a64.c | 35 +++++++++++------------- target/arm/translate.c | 29 ++++++++++---------- target/cris/translate.c | 2 +- target/hppa/translate.c | 63 ++++++++++++++++++++++------------------= ---- target/i386/translate.c | 13 +++++---- target/m68k/translate.c | 14 +++++----- target/mips/translate.c | 2 +- target/nios2/translate.c | 6 ++--- target/ppc/translate.c | 2 +- target/s390x/translate.c | 42 ++++++++++++++--------------- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 10 +++---- target/unicore32/translate.c | 4 +-- tcg/tcg.c | 4 +-- 18 files changed, 122 insertions(+), 143 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 3129159907..ca07b32b65 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -807,8 +807,6 @@ void tcg_gen_lookup_and_goto_ptr(void); #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new() tcg_temp_local_new_i32() #define tcg_temp_free tcg_temp_free_i32 -#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) -#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else @@ -817,8 +815,6 @@ void tcg_gen_lookup_and_goto_ptr(void); #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new() tcg_temp_local_new_i64() #define tcg_temp_free tcg_temp_free_i64 -#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) -#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index cb7b329876..c21194c858 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -428,15 +428,6 @@ typedef TCGv_ptr TCGv_env; #error Unhandled TARGET_LONG_BITS value #endif =20 -/* See the comment before tcgv_i32_temp. */ -#define TCGV_UNUSED_I32(x) (x =3D (TCGv_i32)NULL) -#define TCGV_UNUSED_I64(x) (x =3D (TCGv_i64)NULL) -#define TCGV_UNUSED_PTR(x) (x =3D (TCGv_ptr)NULL) - -#define TCGV_IS_UNUSED_I32(x) ((x) =3D=3D (TCGv_i32)NULL) -#define TCGV_IS_UNUSED_I64(x) ((x) =3D=3D (TCGv_i64)NULL) -#define TCGV_IS_UNUSED_PTR(x) ((x) =3D=3D (TCGv_ptr)NULL) - /* call flags */ /* Helper does not read globals (either directly or through an exception).= It implies TCG_CALL_NO_WRITE_GLOBALS. */ diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 629f35ec8e..73a1b5e63e 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -156,7 +156,7 @@ void alpha_translate_init(void) =20 static TCGv load_zero(DisasContext *ctx) { - if (TCGV_IS_UNUSED_I64(ctx->zero)) { + if (!ctx->zero) { ctx->zero =3D tcg_const_i64(0); } return ctx->zero; @@ -164,7 +164,7 @@ static TCGv load_zero(DisasContext *ctx) =20 static TCGv dest_sink(DisasContext *ctx) { - if (TCGV_IS_UNUSED_I64(ctx->sink)) { + if (!ctx->sink) { ctx->sink =3D tcg_temp_new(); } return ctx->sink; @@ -172,18 +172,18 @@ static TCGv dest_sink(DisasContext *ctx) =20 static void free_context_temps(DisasContext *ctx) { - if (!TCGV_IS_UNUSED_I64(ctx->sink)) { + if (ctx->sink) { tcg_gen_discard_i64(ctx->sink); tcg_temp_free(ctx->sink); - TCGV_UNUSED_I64(ctx->sink); + ctx->sink =3D NULL; } - if (!TCGV_IS_UNUSED_I64(ctx->zero)) { + if (ctx->zero) { tcg_temp_free(ctx->zero); - TCGV_UNUSED_I64(ctx->zero); + ctx->zero =3D NULL; } - if (!TCGV_IS_UNUSED_I64(ctx->lit)) { + if (ctx->lit) { tcg_temp_free(ctx->lit); - TCGV_UNUSED_I64(ctx->lit); + ctx->lit =3D NULL; } } =20 @@ -2948,9 +2948,9 @@ static int alpha_tr_init_disas_context(DisasContextBa= se *dcbase, /* Similarly for flush-to-zero. */ ctx->tb_ftz =3D -1; =20 - TCGV_UNUSED_I64(ctx->zero); - TCGV_UNUSED_I64(ctx->sink); - TCGV_UNUSED_I64(ctx->lit); + ctx->zero =3D NULL; + ctx->sink =3D NULL; + ctx->lit =3D NULL; =20 /* Bound the number of insns to execute to those left on the page. */ if (in_superpage(ctx, ctx->base.pc_first)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 625ef2dfd2..460bab5987 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -405,10 +405,7 @@ static void unallocated_encoding(DisasContext *s) static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG - int i; - for (i =3D 0; i < ARRAY_SIZE(s->tmp_a64); i++) { - TCGV_UNUSED_I64(s->tmp_a64[i]); - } + memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); #endif s->tmp_a64_count =3D 0; } @@ -6276,7 +6273,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) return; } =20 - TCGV_UNUSED_PTR(fpst); + fpst =3D NULL; break; case 0xc: /* FMAXNMP */ case 0xd: /* FADDP */ @@ -6371,7 +6368,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) tcg_temp_free_i32(tcg_res); } =20 - if (!TCGV_IS_UNUSED_PTR(fpst)) { + if (fpst) { tcg_temp_free_ptr(fpst); } } @@ -6387,7 +6384,7 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res,= TCGv_i64 tcg_src, bool is_u, int size, int shift) { bool extended_result =3D false; - bool round =3D !TCGV_IS_UNUSED_I64(tcg_rnd); + bool round =3D tcg_rnd !=3D NULL; int ext_lshift =3D 0; TCGv_i64 tcg_src_hi; =20 @@ -6533,7 +6530,7 @@ static void handle_scalar_simd_shri(DisasContext *s, uint64_t round_const =3D 1ULL << (shift - 1); tcg_round =3D tcg_const_i64(round_const); } else { - TCGV_UNUSED_I64(tcg_round); + tcg_round =3D NULL; } =20 tcg_rn =3D read_fp_dreg(s, rn); @@ -6649,7 +6646,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, uint64_t round_const =3D 1ULL << (shift - 1); tcg_round =3D tcg_const_i64(round_const); } else { - TCGV_UNUSED_I64(tcg_round); + tcg_round =3D NULL; } =20 for (i =3D 0; i < elements; i++) { @@ -8239,8 +8236,8 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(); } else { - TCGV_UNUSED_I32(tcg_rmode); - TCGV_UNUSED_PTR(tcg_fpstatus); + tcg_rmode =3D NULL; + tcg_fpstatus =3D NULL; } =20 if (size =3D=3D 3) { @@ -8360,7 +8357,7 @@ static void handle_vec_simd_shri(DisasContext *s, boo= l is_q, bool is_u, uint64_t round_const =3D 1ULL << (shift - 1); tcg_round =3D tcg_const_i64(round_const); } else { - TCGV_UNUSED_I64(tcg_round); + tcg_round =3D NULL; } =20 for (i =3D 0; i < elements; i++) { @@ -8502,7 +8499,7 @@ static void handle_vec_simd_shrn(DisasContext *s, boo= l is_q, uint64_t round_const =3D 1ULL << (shift - 1); tcg_round =3D tcg_const_i64(round_const); } else { - TCGV_UNUSED_I64(tcg_round); + tcg_round =3D NULL; } =20 for (i =3D 0; i < elements; i++) { @@ -9168,7 +9165,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, if (opcode >=3D 0x58) { fpst =3D get_fpstatus_ptr(); } else { - TCGV_UNUSED_PTR(fpst); + fpst =3D NULL; } =20 if (!fp_access_check(s)) { @@ -9305,7 +9302,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, } } =20 - if (!TCGV_IS_UNUSED_PTR(fpst)) { + if (fpst) { tcg_temp_free_ptr(fpst); } } @@ -10226,13 +10223,13 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) if (need_fpstatus) { tcg_fpstatus =3D get_fpstatus_ptr(); } else { - TCGV_UNUSED_PTR(tcg_fpstatus); + tcg_fpstatus =3D NULL; } if (need_rmode) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); } else { - TCGV_UNUSED_I32(tcg_rmode); + tcg_rmode =3D NULL; } =20 if (size =3D=3D 3) { @@ -10593,7 +10590,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) if (is_fp) { fpst =3D get_fpstatus_ptr(); } else { - TCGV_UNUSED_PTR(fpst); + fpst =3D NULL; } =20 if (size =3D=3D 3) { @@ -10917,7 +10914,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } } =20 - if (!TCGV_IS_UNUSED_PTR(fpst)) { + if (fpst) { tcg_temp_free_ptr(fpst); } } diff --git a/target/arm/translate.c b/target/arm/translate.c index e15192d5d6..46c25ae2c1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2169,8 +2169,8 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) tmp3 =3D tcg_const_i32((insn & 1) << 5); break; default: - TCGV_UNUSED_I32(tmp2); - TCGV_UNUSED_I32(tmp3); + tmp2 =3D NULL; + tmp3 =3D NULL; } gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); tcg_temp_free_i32(tmp3); @@ -4939,7 +4939,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) } } else /* size =3D=3D 0 */ { if (load) { - TCGV_UNUSED_I32(tmp2); + tmp2 =3D NULL; for (n =3D 0; n < 4; n++) { tmp =3D tcg_temp_new_i32(); gen_aa32_ld8u(s, tmp, addr, get_mem_index(= s)); @@ -6643,11 +6643,11 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) tmp =3D neon_load_reg(rn, 1); neon_store_scratch(2, tmp); } - TCGV_UNUSED_I32(tmp3); + tmp3 =3D NULL; for (pass =3D 0; pass < 2; pass++) { if (src1_wide) { neon_load_reg64(cpu_V0, rn + pass); - TCGV_UNUSED_I32(tmp); + tmp =3D NULL; } else { if (pass =3D=3D 1 && rd =3D=3D rn) { tmp =3D neon_load_scratch(2); @@ -6660,7 +6660,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } if (src2_wide) { neon_load_reg64(cpu_V1, rm + pass); - TCGV_UNUSED_I32(tmp2); + tmp2 =3D NULL; } else { if (pass =3D=3D 1 && rd =3D=3D rm) { tmp2 =3D neon_load_scratch(2); @@ -7078,7 +7078,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) if (rm & 1) { return 1; } - TCGV_UNUSED_I32(tmp2); + tmp2 =3D NULL; for (pass =3D 0; pass < 2; pass++) { neon_load_reg64(cpu_V0, rm + pass); tmp =3D tcg_temp_new_i32(); @@ -7217,7 +7217,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) if (neon_2rm_is_float_op(op)) { tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); - TCGV_UNUSED_I32(tmp); + tmp =3D NULL; } else { tmp =3D neon_load_reg(rm, pass); } @@ -8666,7 +8666,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) rn =3D (insn >> 16) & 0xf; tmp =3D load_reg(s, rn); } else { - TCGV_UNUSED_I32(tmp); + tmp =3D NULL; } rd =3D (insn >> 12) & 0xf; switch(op1) { @@ -9505,7 +9505,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) =20 /* compute total size */ loaded_base =3D 0; - TCGV_UNUSED_I32(loaded_var); + loaded_var =3D NULL; n =3D 0; for(i=3D0;i<16;i++) { if (insn & (1 << i)) @@ -10074,7 +10074,7 @@ static int disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) tcg_gen_addi_i32(addr, addr, -offset); } =20 - TCGV_UNUSED_I32(loaded_var); + loaded_var =3D NULL; for (i =3D 0; i < 16; i++) { if ((insn & (1 << i)) =3D=3D 0) continue; @@ -11355,7 +11355,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) } else if (op !=3D 0xf) { /* mvn doesn't read its first operand */ tmp =3D load_reg(s, rd); } else { - TCGV_UNUSED_I32(tmp); + tmp =3D NULL; } =20 tmp2 =3D load_reg(s, rm); @@ -11686,7 +11686,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) tcg_gen_addi_i32(addr, addr, 4); } } - TCGV_UNUSED_I32(tmp); + tmp =3D NULL; if (insn & (1 << 8)) { if (insn & (1 << 11)) { /* pop pc */ @@ -11831,8 +11831,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) case 12: { /* load/store multiple */ - TCGv_i32 loaded_var; - TCGV_UNUSED_I32(loaded_var); + TCGv_i32 loaded_var =3D NULL; rn =3D (insn >> 8) & 0x7; addr =3D load_reg(s, rn); for (i =3D 0; i < 8; i++) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 2831419845..74822ed31f 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2603,7 +2603,7 @@ static int dec_movem_mr(CPUCRISState *env, DisasConte= xt *dc) tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); gen_load(dc, tmp32, addr, 4, 0); } else { - TCGV_UNUSED(tmp32); + tmp32 =3D NULL; } tcg_temp_free(addr); =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 53aa1f88c4..31d9a2a31b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -125,7 +125,7 @@ void hppa_translate_init(void) =20 int i; =20 - TCGV_UNUSED(cpu_gr[0]); + cpu_gr[0] =3D NULL; for (i =3D 1; i < 32; i++) { cpu_gr[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUHPPAState, gr[i]), @@ -140,28 +140,31 @@ void hppa_translate_init(void) =20 static DisasCond cond_make_f(void) { - DisasCond r =3D { .c =3D TCG_COND_NEVER }; - TCGV_UNUSED(r.a0); - TCGV_UNUSED(r.a1); - return r; + return (DisasCond){ + .c =3D TCG_COND_NEVER, + .a0 =3D NULL, + .a1 =3D NULL, + }; } =20 static DisasCond cond_make_n(void) { - DisasCond r =3D { .c =3D TCG_COND_NE, .a0_is_n =3D true, .a1_is_0 =3D = true }; - r.a0 =3D cpu_psw_n; - TCGV_UNUSED(r.a1); - return r; + return (DisasCond){ + .c =3D TCG_COND_NE, + .a0 =3D cpu_psw_n, + .a0_is_n =3D true, + .a1 =3D NULL, + .a1_is_0 =3D true + }; } =20 static DisasCond cond_make_0(TCGCond c, TCGv a0) { - DisasCond r =3D { .c =3D c, .a1_is_0 =3D true }; + DisasCond r =3D { .c =3D c, .a1 =3D NULL, .a1_is_0 =3D true }; =20 assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); r.a0 =3D tcg_temp_new(); tcg_gen_mov_tl(r.a0, a0); - TCGV_UNUSED(r.a1); =20 return r; } @@ -199,8 +202,8 @@ static void cond_free(DisasCond *cond) } cond->a0_is_n =3D false; cond->a1_is_0 =3D false; - TCGV_UNUSED(cond->a0); - TCGV_UNUSED(cond->a1); + cond->a0 =3D NULL; + cond->a1 =3D NULL; /* fallthru */ case TCG_COND_ALWAYS: cond->c =3D TCG_COND_NEVER; @@ -716,9 +719,8 @@ static DisasCond do_sed_cond(unsigned orig, TCGv res) static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2) { DisasCond cond; - TCGv tmp, cb; + TCGv tmp, cb =3D NULL; =20 - TCGV_UNUSED(cb); if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not * do our normal thing and compute carry-in of bit B+1 since that @@ -826,8 +828,8 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned= rt, TCGv in1, TCGv in2, DisasCond cond; =20 dest =3D tcg_temp_new(); - TCGV_UNUSED(cb); - TCGV_UNUSED(cb_msb); + cb =3D NULL; + cb_msb =3D NULL; =20 if (shift) { tmp =3D get_temp(ctx); @@ -856,7 +858,7 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned= rt, TCGv in1, TCGv in2, } =20 /* Compute signed overflow if required. */ - TCGV_UNUSED(sv); + sv =3D NULL; if (is_tsv || c =3D=3D 6) { sv =3D do_add_sv(ctx, dest, in1, in2); if (is_tsv) { @@ -919,7 +921,7 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned= rt, TCGv in1, TCGv in2, tcg_temp_free(zero); =20 /* Compute signed overflow if required. */ - TCGV_UNUSED(sv); + sv =3D NULL; if (is_tsv || c =3D=3D 6) { sv =3D do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { @@ -965,7 +967,7 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsig= ned rt, TCGv in1, tcg_gen_sub_tl(dest, in1, in2); =20 /* Compute signed overflow if required. */ - TCGV_UNUSED(sv); + sv =3D NULL; if ((cf >> 1) =3D=3D 6) { sv =3D do_sub_sv(ctx, dest, in1, in2); } @@ -2070,8 +2072,7 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint= 32_t insn, =20 /* Install the new nullification. */ if (cf) { - TCGv sv; - TCGV_UNUSED(sv); + TCGv sv =3D NULL; if (cf >> 1 =3D=3D 6) { /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); @@ -2542,7 +2543,7 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, ui= nt32_t insn, =20 tcg_gen_sub_tl(dest, in1, in2); =20 - TCGV_UNUSED(sv); + sv =3D NULL; if (c =3D=3D 6) { sv =3D do_sub_sv(ctx, dest, in1, in2); } @@ -2571,8 +2572,8 @@ static DisasJumpType trans_addb(DisasContext *ctx, ui= nt32_t insn, } in2 =3D load_gpr(ctx, r); dest =3D dest_gpr(ctx, r); - TCGV_UNUSED(sv); - TCGV_UNUSED(cb_msb); + sv =3D NULL; + cb_msb =3D NULL; =20 switch (c) { default: @@ -3732,18 +3733,16 @@ static int hppa_tr_init_disas_context(DisasContextB= ase *dcbase, { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); TranslationBlock *tb =3D ctx->base.tb; - int i, bound; + int bound; =20 ctx->cs =3D cs; ctx->iaoq_f =3D tb->pc; ctx->iaoq_b =3D tb->cs_base; ctx->iaoq_n =3D -1; - TCGV_UNUSED(ctx->iaoq_n_var); + ctx->iaoq_n_var =3D NULL; =20 ctx->ntemps =3D 0; - for (i =3D 0; i < ARRAY_SIZE(ctx->temps); ++i) { - TCGV_UNUSED(ctx->temps[i]); - } + memset(ctx->temps, 0, sizeof(ctx->temps)); =20 bound =3D -(tb->pc | TARGET_PAGE_MASK) / 4; return MIN(max_insns, bound); @@ -3804,7 +3803,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; - TCGV_UNUSED(ctx->iaoq_n_var); + ctx->iaoq_n_var =3D NULL; } =20 if (unlikely(ctx->null_cond.c =3D=3D TCG_COND_ALWAYS)) { @@ -3819,7 +3818,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) /* Free any temporaries allocated. */ for (i =3D 0, n =3D ctx->ntemps; i < n; ++i) { tcg_temp_free(ctx->temps[i]); - TCGV_UNUSED(ctx->temps[i]); + ctx->temps[i] =3D NULL; } ctx->ntemps =3D 0; =20 diff --git a/target/i386/translate.c b/target/i386/translate.c index 088a9d9766..8c5f12985a 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -689,7 +689,7 @@ static void gen_compute_eflags(DisasContext *s) return; } =20 - TCGV_UNUSED(zero); + zero =3D NULL; dst =3D cpu_cc_dst; src1 =3D cpu_cc_src; src2 =3D cpu_cc_src2; @@ -2050,9 +2050,8 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env,= DisasContext *s, /* Compute the address, with a minimum number of TCG ops. */ static TCGv gen_lea_modrm_1(AddressParts a) { - TCGv ea; + TCGv ea =3D NULL; =20 - TCGV_UNUSED(ea); if (a.index >=3D 0) { if (a.scale =3D=3D 0) { ea =3D cpu_regs[a.index]; @@ -2067,7 +2066,7 @@ static TCGv gen_lea_modrm_1(AddressParts a) } else if (a.base >=3D 0) { ea =3D cpu_regs[a.base]; } - if (TCGV_IS_UNUSED(ea)) { + if (!ea) { tcg_gen_movi_tl(cpu_A0, a.disp); ea =3D cpu_A0; } else if (a.disp !=3D 0) { @@ -3951,7 +3950,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); =20 /* Re-use the carry-out from a previous round. */ - TCGV_UNUSED(carry_in); + carry_in =3D NULL; carry_out =3D (b =3D=3D 0x1f6 ? cpu_cc_dst : cpu_cc_sr= c2); switch (s->cc_op) { case CC_OP_ADCX: @@ -3979,7 +3978,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, break; } /* If we can't reuse carry-out, get it out of EFLAGS. = */ - if (TCGV_IS_UNUSED(carry_in)) { + if (!carry_in) { if (s->cc_op !=3D CC_OP_ADCX && s->cc_op !=3D CC_O= P_ADOX) { gen_compute_eflags(s); } @@ -7672,7 +7671,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) tcg_gen_mov_tl(a0, cpu_A0); } else { gen_op_mov_v_reg(ot, t0, rm); - TCGV_UNUSED(a0); + a0 =3D NULL; } gen_op_mov_v_reg(ot, t1, reg); tcg_gen_andi_tl(cpu_tmp0, t0, 3); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b60909222c..e78c9f208b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -3956,8 +3956,8 @@ DISAS_INSN(bfop_reg) int ofs =3D extract32(ext, 6, 5); /* big bit-endian */ TCGv mask, tofs, tlen; =20 - TCGV_UNUSED(tofs); - TCGV_UNUSED(tlen); + tofs =3D NULL; + tlen =3D NULL; if ((insn & 0x0f00) =3D=3D 0x0d00) { /* bfffo */ tofs =3D tcg_temp_new(); tlen =3D tcg_temp_new(); @@ -3973,7 +3973,7 @@ DISAS_INSN(bfop_reg) } tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski); mask =3D tcg_const_i32(ror32(maski, ofs)); - if (!TCGV_IS_UNUSED(tofs)) { + if (tofs) { tcg_gen_movi_i32(tofs, ofs); tcg_gen_movi_i32(tlen, len); } @@ -3985,13 +3985,13 @@ DISAS_INSN(bfop_reg) tcg_gen_andi_i32(tmp, tmp, 31); mask =3D tcg_const_i32(0x7fffffffu); tcg_gen_shr_i32(mask, mask, tmp); - if (!TCGV_IS_UNUSED(tlen)) { + if (tlen) { tcg_gen_addi_i32(tlen, tmp, 1); } } else { /* Immediate width */ mask =3D tcg_const_i32(0x7fffffffu >> (len - 1)); - if (!TCGV_IS_UNUSED(tlen)) { + if (tlen) { tcg_gen_movi_i32(tlen, len); } } @@ -4001,7 +4001,7 @@ DISAS_INSN(bfop_reg) tcg_gen_rotl_i32(QREG_CC_N, src, tmp); tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); tcg_gen_rotr_i32(mask, mask, tmp); - if (!TCGV_IS_UNUSED(tofs)) { + if (tofs) { tcg_gen_mov_i32(tofs, tmp); } } else { @@ -4009,7 +4009,7 @@ DISAS_INSN(bfop_reg) tcg_gen_rotli_i32(QREG_CC_N, src, ofs); tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); tcg_gen_rotri_i32(mask, mask, ofs); - if (!TCGV_IS_UNUSED(tofs)) { + if (tofs) { tcg_gen_movi_i32(tofs, ofs); } } diff --git a/target/mips/translate.c b/target/mips/translate.c index b022f840c9..d05ee67e63 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20453,7 +20453,7 @@ void mips_tcg_init(void) { int i; =20 - TCGV_UNUSED(cpu_gpr[0]); + cpu_gpr[0] =3D NULL; for (i =3D 1; i < 32; i++) cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.g= pr[i]), diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 72329002ac..0afd10f08a 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -124,7 +124,7 @@ static uint8_t get_opxcode(uint32_t code) =20 static TCGv load_zero(DisasContext *dc) { - if (TCGV_IS_UNUSED_I32(dc->zero)) { + if (!dc->zero) { dc->zero =3D tcg_const_i32(0); } return dc->zero; @@ -754,12 +754,12 @@ static void handle_instruction(DisasContext *dc, CPUN= ios2State *env) goto illegal_op; } =20 - TCGV_UNUSED_I32(dc->zero); + dc->zero =3D NULL; =20 instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); =20 - if (!TCGV_IS_UNUSED_I32(dc->zero)) { + if (dc->zero) { tcg_temp_free(dc->zero); } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4075fc8589..0ef21cce33 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3495,7 +3495,7 @@ static void gen_bcond(DisasContext *ctx, int type) else tcg_gen_mov_tl(target, cpu_lr); } else { - TCGV_UNUSED(target); + target =3D NULL; } if (LK(ctx->opcode)) gen_setlr(ctx, ctx->nip); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index eede2ed157..ac55886792 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -434,11 +434,9 @@ static void set_cc_static(DisasContext *s) /* calculates cc into cc_op */ static void gen_op_calc_cc(DisasContext *s) { - TCGv_i32 local_cc_op; - TCGv_i64 dummy; + TCGv_i32 local_cc_op =3D NULL; + TCGv_i64 dummy =3D NULL; =20 - TCGV_UNUSED_I32(local_cc_op); - TCGV_UNUSED_I64(dummy); switch (s->cc_op) { default: dummy =3D tcg_const_i64(0); @@ -528,10 +526,10 @@ static void gen_op_calc_cc(DisasContext *s) tcg_abort(); } =20 - if (!TCGV_IS_UNUSED_I32(local_cc_op)) { + if (local_cc_op) { tcg_temp_free_i32(local_cc_op); } - if (!TCGV_IS_UNUSED_I64(dummy)) { + if (dummy) { tcg_temp_free_i64(dummy); } =20 @@ -1189,7 +1187,7 @@ static ExitStatus help_branch(DisasContext *s, DisasC= ompare *c, goto egress; } } else { - if (TCGV_IS_UNUSED_I64(cdest)) { + if (!cdest) { /* E.g. bcr %r0 -> no branch. */ ret =3D NO_EXIT; goto egress; @@ -1451,7 +1449,7 @@ static ExitStatus op_ni(DisasContext *s, DisasOps *o) static ExitStatus op_bas(DisasContext *s, DisasOps *o) { tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc)); - if (!TCGV_IS_UNUSED_I64(o->in2)) { + if (o->in2) { tcg_gen_mov_i64(psw_addr, o->in2); per_branch(s, false); return EXIT_PC_UPDATED; @@ -3031,7 +3029,7 @@ static ExitStatus op_mov2(DisasContext *s, DisasOps *= o) { o->out =3D o->in2; o->g_out =3D o->g_in2; - TCGV_UNUSED_I64(o->in2); + o->in2 =3D NULL; o->g_in2 =3D false; return NO_EXIT; } @@ -3043,7 +3041,7 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps = *o) =20 o->out =3D o->in2; o->g_out =3D o->g_in2; - TCGV_UNUSED_I64(o->in2); + o->in2 =3D NULL; o->g_in2 =3D false; =20 switch (s->tb->flags & FLAG_MASK_ASC) { @@ -3077,8 +3075,8 @@ static ExitStatus op_movx(DisasContext *s, DisasOps *= o) o->out2 =3D o->in2; o->g_out =3D o->g_in1; o->g_out2 =3D o->g_in2; - TCGV_UNUSED_I64(o->in1); - TCGV_UNUSED_I64(o->in2); + o->in1 =3D NULL; + o->in2 =3D NULL; o->g_in1 =3D o->g_in2 =3D false; return NO_EXIT; } @@ -5945,11 +5943,11 @@ static ExitStatus translate_one(CPUS390XState *env,= DisasContext *s) s->insn =3D insn; s->fields =3D &f; o.g_out =3D o.g_out2 =3D o.g_in1 =3D o.g_in2 =3D false; - TCGV_UNUSED_I64(o.out); - TCGV_UNUSED_I64(o.out2); - TCGV_UNUSED_I64(o.in1); - TCGV_UNUSED_I64(o.in2); - TCGV_UNUSED_I64(o.addr1); + o.out =3D NULL; + o.out2 =3D NULL; + o.in1 =3D NULL; + o.in2 =3D NULL; + o.addr1 =3D NULL; =20 /* Implement the instruction. */ if (insn->help_in1) { @@ -5972,19 +5970,19 @@ static ExitStatus translate_one(CPUS390XState *env,= DisasContext *s) } =20 /* Free any temporaries created by the helpers. */ - if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) { + if (o.out && !o.g_out) { tcg_temp_free_i64(o.out); } - if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) { + if (o.out2 && !o.g_out2) { tcg_temp_free_i64(o.out2); } - if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) { + if (o.in1 && !o.g_in1) { tcg_temp_free_i64(o.in1); } - if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) { + if (o.in2 && !o.g_in2) { tcg_temp_free_i64(o.in2); } - if (!TCGV_IS_UNUSED_I64(o.addr1)) { + if (o.addr1) { tcg_temp_free_i64(o.addr1); } =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 703020fe87..48ea0fe7e0 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1901,7 +1901,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) op_dst =3D op_src =3D op_opc =3D -1; mt_dst =3D -1; st_src =3D st_mop =3D -1; - TCGV_UNUSED(op_arg); + op_arg =3D NULL; i =3D 0; =20 #define NEXT_INSN \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 849a02aebd..71e0853e43 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5922,7 +5922,7 @@ void sparc_tcg_init(void) *rtl[i].ptr =3D tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].nam= e); } =20 - TCGV_UNUSED(cpu_regs[0]); + cpu_regs[0] =3D NULL; for (i =3D 1; i < 8; ++i) { cpu_regs[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUSPARCState, gregs[i]), diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index d55549dabc..d63bf5bba3 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -143,7 +143,7 @@ static bool check_gr(DisasContext *dc, uint8_t reg) =20 static TCGv load_zero(DisasContext *dc) { - if (TCGV_IS_UNUSED_I64(dc->zero)) { + if (!dc->zero) { dc->zero =3D tcg_const_i64(0); } return dc->zero; @@ -2324,7 +2324,7 @@ static void translate_one_bundle(DisasContext *dc, ui= nt64_t bundle) for (i =3D 0; i < ARRAY_SIZE(dc->wb); i++) { DisasContextTemp *wb =3D &dc->wb[i]; wb->reg =3D TILEGX_R_NOREG; - TCGV_UNUSED_I64(wb->val); + wb->val =3D NULL; } dc->num_wb =3D 0; =20 @@ -2384,9 +2384,9 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) dc->exit_tb =3D false; dc->atomic_excp =3D TILEGX_EXCP_NONE; dc->jmp.cond =3D TCG_COND_NEVER; - TCGV_UNUSED_I64(dc->jmp.dest); - TCGV_UNUSED_I64(dc->jmp.val1); - TCGV_UNUSED_I64(dc->zero); + dc->jmp.dest =3D NULL; + dc->jmp.val1 =3D NULL; + dc->zero =3D NULL; =20 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log_lock(); diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 384aa86027..5b51f2166d 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1230,7 +1230,7 @@ static void do_datap(CPUUniCore32State *env, DisasCon= text *s, uint32_t insn) if (UCOP_OPCODES !=3D 0x0f && UCOP_OPCODES !=3D 0x0d) { tmp =3D load_reg(s, UCOP_REG_N); } else { - TCGV_UNUSED(tmp); + tmp =3D NULL; } =20 switch (UCOP_OPCODES) { @@ -1652,7 +1652,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasCo= ntext *s, uint32_t insn) =20 /* compute total size */ loaded_base =3D 0; - TCGV_UNUSED(loaded_var); + loaded_var =3D NULL; n =3D 0; for (i =3D 0; i < 6; i++) { if (UCOP_SET(i)) { diff --git a/tcg/tcg.c b/tcg/tcg.c index c22f1c4441..68bcd2267b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1358,8 +1358,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) TCGv_i64 retl, reth; TCGTemp *split_args[MAX_OPC_PARAM]; =20 - TCGV_UNUSED_I64(retl); - TCGV_UNUSED_I64(reth); + retl =3D NULL; + reth =3D NULL; if (sizemask !=3D 0) { for (i =3D real_args =3D 0; i < nargs; ++i) { int is_64bit =3D sizemask & (1 << (i+1)*2); --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513357930355608.5315914306511; Fri, 15 Dec 2017 09:12:10 -0800 (PST) Received: from localhost ([::1]:47800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtWm-0004pS-Bn for importer@patchew.org; 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[141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=a/jldLi2ua7n0zGBy6Y91I3cHXFRmFrFWp2Cth96bNg=; b=ZJQHniC0FXWY0NcHnHoGX/BSzH8NPd+YKZCWPVTk1Ke0EfWA0ObM2CVApEM6wg6ezL 1OdlqrsZgza67oBzuXX7jdbjVvPkv2HXlPj+6puLwtjAPWExYyLCsGQqqccT/ZH+SDxQ d/xV6nYn7bBP499JW/HaweSA7MA3NIlFhj/KE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=a/jldLi2ua7n0zGBy6Y91I3cHXFRmFrFWp2Cth96bNg=; b=iCPq9TpsqPN2KE6xPi0CbgwQHiBfvnLIj1QHbG/99sd96nfZW5foR3uNUzRtr28nF/ 1zuqT02S32emc8CaG13kvFP+NEB6OQ3poA354ptaEuNB2T4GNqYsogKM3/RcORSVYks+ Bkhr+X0fTRCvp78nSJ4hRnqz1W6AlGwsNh1riR7d5FC2yxQY6i1tE3AiCJWN4ulUhoRG K8eZ3Pc7mj/HzwEG6J9Q1CqgeDDVbL1LTPbMzZEUJmV7L3EhirHrgTDX+zVI5V43h14h Z0n/tuwPyn95I2kn0TMRMPYpdHpNdN1spwIRj9wSt3wHnivPaEjZhPmgbBZwOMi0QUmZ l6Yg== X-Gm-Message-State: AKGB3mKO9DUSb6Hdh36uNpNES/SX0FeNP+8goj/6vu2XKalNQP0BnI89 yF6tYlfpBxRZEXY1mSrSqC1o/j6GayY= X-Google-Smtp-Source: ACJfBou1pw66VTqI4aBTDqhh8zBF7FxEqTciYD0SJRwSz0FkBoM+6R8RxrdDBi6JudON/HuC7ZlKyg== X-Received: by 10.36.154.68 with SMTP id l65mr9622719ite.150.1513357663957; Fri, 15 Dec 2017 09:07:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:29 -0600 Message-Id: <20171215170732.31125-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 4/7] tcg: Dynamically allocate TCGOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With no fixed array allocation, we can't overflow a buffer. This will be important as optimizations related to host vectors may expand the number of ops used. Use QTAILQ to link the ops together. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 9 ++-- include/qemu/queue.h | 5 ++ target/arm/translate.h | 10 ++-- tcg/tcg.h | 35 +++++------- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 - target/lm32/translate.c | 2 - target/microblaze/translate.c | 4 -- tcg/optimize.c | 16 ++---- tcg/tcg-op.c | 24 --------- tcg/tcg.c | 123 ++++++++++++++++----------------------= ---- 12 files changed, 77 insertions(+), 157 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 049bba86e9..54aaa61d65 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,7 +5,7 @@ =20 /* Helpers for instruction counting code generation. */ =20 -static int icount_start_insn_idx; +static TCGOp *icount_start_insn; =20 static inline void gen_tb_start(TranslationBlock *tb) { @@ -26,8 +26,8 @@ static inline void gen_tb_start(TranslationBlock *tb) /* We emit a movi with a dummy immediate argument. Keep the insn i= ndex * of the movi so that we later (when we know the actual insn coun= t) * can update the immediate argument with the actual insn count. = */ - icount_start_insn_idx =3D tcg_op_buf_count(); tcg_gen_movi_i32(imm, 0xdeadbeef); + icount_start_insn =3D tcg_last_op(); =20 tcg_gen_sub_i32(count, count, imm); tcg_temp_free_i32(imm); @@ -48,14 +48,11 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know * the actual insn count. */ - tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); + tcg_set_insn_param(icount_start_insn, 1, num_insns); } =20 gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); - - /* Terminate the linked list. */ - tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next =3D 0; } =20 static inline void gen_io_start(void) diff --git a/include/qemu/queue.h b/include/qemu/queue.h index 35292c3155..aa270d2b38 100644 --- a/include/qemu/queue.h +++ b/include/qemu/queue.h @@ -425,6 +425,11 @@ struct { = \ (var); \ (var) =3D (*(((struct headname *)((var)->field.tqe_prev))-= >tqh_last))) =20 +#define QTAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, prev_var) \ + for ((var) =3D (*(((struct headname *)((head)->tqh_last))->tqh_las= t)); \ + (var) && ((prev_var) =3D (*(((struct headname *)((var)->field= .tqe_prev))->tqh_last)), 1); \ + (var) =3D (prev_var)) + /* * Tail queue access methods. */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 410ba79c0d..cd7313ace7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -66,8 +66,8 @@ typedef struct DisasContext { bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; - /* TCG op index of the current insn_start. */ - int insn_start_idx; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; #define TMP_A64_MAX 16 int tmp_a64_count; TCGv_i64 tmp_a64[TMP_A64_MAX]; @@ -117,9 +117,9 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) syn >>=3D ARM_INSN_START_WORD2_SHIFT; =20 /* We check and clear insn_start_idx to catch multiple updates. */ - assert(s->insn_start_idx !=3D 0); - tcg_set_insn_param(s->insn_start_idx, 2, syn); - s->insn_start_idx =3D 0; + assert(s->insn_start !=3D NULL); + tcg_set_insn_param(s->insn_start, 2, syn); + s->insn_start =3D NULL; } =20 /* is_jmp field values */ diff --git a/tcg/tcg.h b/tcg/tcg.h index c21194c858..a577447846 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -29,6 +29,7 @@ #include "cpu.h" #include "exec/tb-context.h" #include "qemu/bitops.h" +#include "qemu/queue.h" #include "tcg-mo.h" #include "tcg-target.h" =20 @@ -48,8 +49,6 @@ * and up to 4 + N parameters on 64-bit archs * (N =3D number of input arguments + output arguments). */ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) -#define OPC_BUF_SIZE 640 -#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) =20 #define CPU_TEMP_BUF_NLONGS 128 =20 @@ -572,23 +571,18 @@ typedef struct TCGOp { unsigned callo : 2; /* 14 */ unsigned : 2; /* 16 */ =20 - /* Index of the prev/next op, or 0 for the end of the list. */ - unsigned prev : 16; /* 32 */ - unsigned next : 16; /* 48 */ - /* Lifetime data of the operands. */ - unsigned life : 16; /* 64 */ + unsigned life : 16; /* 32 */ + + /* Next and previous opcodes. */ + QTAILQ_ENTRY(TCGOp) link; =20 /* Arguments for the opcode. */ TCGArg args[MAX_OPC_PARAM]; } TCGOp; =20 -/* Make sure that we don't expand the structure without noticing. */ -QEMU_BUILD_BUG_ON(sizeof(TCGOp) !=3D 8 + sizeof(TCGArg) * MAX_OPC_PARAM); - /* Make sure operands fit in the bitfields above. */ QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); -QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16)); =20 typedef struct TCGProfile { int64_t tb_count1; @@ -642,8 +636,6 @@ struct TCGContext { int goto_tb_issue_mask; #endif =20 - int gen_next_op_idx; - /* Code generation. Note that we specifically do not use tcg_insn_unit here, because there's too much arithmetic throughout that relies on addition and subtraction working on bytes. Rely on the GCC @@ -674,12 +666,12 @@ struct TCGContext { TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 + QTAILQ_HEAD(TCGOpHead, TCGOp) ops, free_ops; + /* Tells which temporary holds a given register. It does not take into account fixed registers */ TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; =20 - TCGOp gen_op_buf[OPC_BUF_SIZE]; - uint16_t gen_insn_end_off[TCG_MAX_INSNS]; target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; @@ -769,21 +761,21 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) } #endif =20 -static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) +static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) { - tcg_ctx->gen_op_buf[op_idx].args[arg] =3D v; + op->args[arg] =3D v; } =20 -/* The number of opcodes emitted so far. */ -static inline int tcg_op_buf_count(void) +/* The last op that was emitted. */ +static inline TCGOp *tcg_last_op(void) { - return tcg_ctx->gen_next_op_idx; + return QTAILQ_LAST(&tcg_ctx->ops, TCGOpHead); } =20 /* Test for whether to terminate the TB for using too many opcodes. */ static inline bool tcg_op_buf_full(void) { - return tcg_op_buf_count() >=3D OPC_MAX_SIZE; + return false; } =20 /* pool based memory allocation */ @@ -967,6 +959,7 @@ bool tcg_op_supported(TCGOpcode op); =20 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); =20 +TCGOp *tcg_emit_op(TCGOpcode opc); void tcg_op_remove(TCGContext *s, TCGOp *op); TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int n= arg); TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int na= rg); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 460bab5987..ba94f7d045 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11290,8 +11290,8 @@ static void aarch64_tr_insn_start(DisasContextBase = *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); + dc->insn_start =3D tcg_last_op(); } =20 static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, diff --git a/target/arm/translate.c b/target/arm/translate.c index 46c25ae2c1..c690658493 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12096,10 +12096,10 @@ static void arm_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), 0); + dc->insn_start =3D tcg_last_op(); } =20 static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, diff --git a/target/cris/translate.c b/target/cris/translate.c index 74822ed31f..f51a731db9 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3297,8 +3297,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(cs, pc_start, dc->pc - pc_start); - qemu_log("\nisize=3D%d osize=3D%d\n", - dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); } #endif diff --git a/target/lm32/translate.c b/target/lm32/translate.c index b8b2b13e36..2e1c5e6d01 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1156,8 +1156,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) qemu_log_lock(); qemu_log("\n"); log_target_disas(cs, pc_start, dc->pc - pc_start); - qemu_log("\nisize=3D%d osize=3D%d\n", - dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); } #endif diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index e7b5597c46..7628b0e25b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1808,11 +1808,7 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("--------------\n"); -#if DISAS_GNU log_target_disas(cs, pc_start, dc->pc - pc_start); -#endif - qemu_log("\nisize=3D%d osize=3D%d\n", - dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); } #endif diff --git a/tcg/optimize.c b/tcg/optimize.c index 438321c6cc..e495680e95 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -602,8 +602,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { - int oi, oi_next, nb_temps, nb_globals; - TCGOp *prev_mb =3D NULL; + int nb_temps, nb_globals; + TCGOp *op, *op_next, *prev_mb =3D NULL; struct tcg_temp_info *infos; TCGTempSet temps_used; =20 @@ -617,17 +617,13 @@ void tcg_optimize(TCGContext *s) bitmap_zero(temps_used.l, nb_temps); infos =3D tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps); =20 - for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { + QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { tcg_target_ulong mask, partmask, affected; int nb_oargs, nb_iargs, i; TCGArg tmp; - - TCGOp * const op =3D &s->gen_op_buf[oi]; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 - oi_next =3D op->next; - /* Count the arguments, and initialize the temps that are going to be used */ if (opc =3D=3D INDEX_op_call) { @@ -1261,9 +1257,6 @@ void tcg_optimize(TCGContext *s) rh =3D op->args[1]; tcg_opt_gen_movi(s, op, rl, (int32_t)a); tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32)); - - /* We've done all we need to do with the movi. Skip it. = */ - oi_next =3D op2->next; break; } goto do_default; @@ -1280,9 +1273,6 @@ void tcg_optimize(TCGContext *s) rh =3D op->args[1]; tcg_opt_gen_movi(s, op, rl, (int32_t)r); tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32)); - - /* We've done all we need to do with the movi. Skip it. = */ - oi_next =3D op2->next; break; } goto do_default; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3cad30b1f2..0c509bfe46 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -42,30 +42,6 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); #define TCGV_HIGH TCGV_HIGH_link_error #endif =20 -/* Note that this is optimized for sequential allocation during translate. - Up to and including filling in the forward link immediately. We'll do - proper termination of the end of the list after we finish translation. = */ - -static inline TCGOp *tcg_emit_op(TCGOpcode opc) -{ - TCGContext *ctx =3D tcg_ctx; - int oi =3D ctx->gen_next_op_idx; - int ni =3D oi + 1; - int pi =3D oi - 1; - TCGOp *op =3D &ctx->gen_op_buf[oi]; - - tcg_debug_assert(oi < OPC_BUF_SIZE); - ctx->gen_op_buf[0].prev =3D oi; - ctx->gen_next_op_idx =3D ni; - - memset(op, 0, offsetof(TCGOp, args)); - op->opc =3D opc; - op->prev =3D pi; - op->next =3D ni; - - return op; -} - void tcg_gen_op1(TCGOpcode opc, TCGArg a1) { TCGOp *op =3D tcg_emit_op(opc); diff --git a/tcg/tcg.c b/tcg/tcg.c index 68bcd2267b..f26949a900 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -862,9 +862,8 @@ void tcg_func_start(TCGContext *s) s->goto_tb_issue_mask =3D 0; #endif =20 - s->gen_op_buf[0].next =3D 1; - s->gen_op_buf[0].prev =3D 0; - s->gen_next_op_idx =3D 1; + QTAILQ_INIT(&s->ops); + QTAILQ_INIT(&s->free_ops); } =20 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -1339,7 +1338,6 @@ bool tcg_op_supported(TCGOpcode op) and endian swap in tcg_reg_alloc_call(). */ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { - TCGContext *s =3D tcg_ctx; int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; @@ -1395,17 +1393,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) } #endif /* TCG_TARGET_EXTEND_ARGS */ =20 - i =3D s->gen_next_op_idx; - tcg_debug_assert(i < OPC_BUF_SIZE); - s->gen_op_buf[0].prev =3D i; - s->gen_next_op_idx =3D i + 1; - op =3D &s->gen_op_buf[i]; - - /* Set links for sequential allocation during translation. */ - memset(op, 0, offsetof(TCGOp, args)); - op->opc =3D INDEX_op_call; - op->prev =3D i - 1; - op->next =3D i + 1; + op =3D tcg_emit_op(INDEX_op_call); =20 pi =3D 0; if (ret !=3D NULL) { @@ -1622,20 +1610,18 @@ void tcg_dump_ops(TCGContext *s) { char buf[128]; TCGOp *op; - int oi; =20 - for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D op->next) { + QTAILQ_FOREACH(op, &s->ops, link) { int i, k, nb_oargs, nb_iargs, nb_cargs; const TCGOpDef *def; TCGOpcode c; int col =3D 0; =20 - op =3D &s->gen_op_buf[oi]; c =3D op->opc; def =3D &tcg_op_defs[c]; =20 if (c =3D=3D INDEX_op_insn_start) { - col +=3D qemu_log("%s ----", oi !=3D s->gen_op_buf[0].next ? "= \n" : ""); + col +=3D qemu_log("\n ----"); =20 for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { target_ulong a; @@ -1898,65 +1884,51 @@ static void process_op_defs(TCGContext *s) =20 void tcg_op_remove(TCGContext *s, TCGOp *op) { - int next =3D op->next; - int prev =3D op->prev; - - /* We should never attempt to remove the list terminator. */ - tcg_debug_assert(op !=3D &s->gen_op_buf[0]); - - s->gen_op_buf[next].prev =3D prev; - s->gen_op_buf[prev].next =3D next; - - memset(op, 0, sizeof(*op)); + QTAILQ_REMOVE(&s->ops, op, link); + QTAILQ_INSERT_TAIL(&s->free_ops, op, link); =20 #ifdef CONFIG_PROFILER atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); #endif } =20 -TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, - TCGOpcode opc, int nargs) +static TCGOp *tcg_op_alloc(TCGOpcode opc) { - int oi =3D s->gen_next_op_idx; - int prev =3D old_op->prev; - int next =3D old_op - s->gen_op_buf; - TCGOp *new_op; + TCGContext *s =3D tcg_ctx; + TCGOp *op; =20 - tcg_debug_assert(oi < OPC_BUF_SIZE); - s->gen_next_op_idx =3D oi + 1; + if (likely(QTAILQ_EMPTY(&s->free_ops))) { + op =3D tcg_malloc(sizeof(TCGOp)); + } else { + op =3D QTAILQ_FIRST(&s->free_ops); + QTAILQ_REMOVE(&s->free_ops, op, link); + } + memset(op, 0, offsetof(TCGOp, link)); + op->opc =3D opc; =20 - new_op =3D &s->gen_op_buf[oi]; - *new_op =3D (TCGOp){ - .opc =3D opc, - .prev =3D prev, - .next =3D next - }; - s->gen_op_buf[prev].next =3D oi; - old_op->prev =3D oi; + return op; +} + +TCGOp *tcg_emit_op(TCGOpcode opc) +{ + TCGOp *op =3D tcg_op_alloc(opc); + QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); + return op; +} =20 +TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, + TCGOpcode opc, int nargs) +{ + TCGOp *new_op =3D tcg_op_alloc(opc); + QTAILQ_INSERT_BEFORE(old_op, new_op, link); return new_op; } =20 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, TCGOpcode opc, int nargs) { - int oi =3D s->gen_next_op_idx; - int prev =3D old_op - s->gen_op_buf; - int next =3D old_op->next; - TCGOp *new_op; - - tcg_debug_assert(oi < OPC_BUF_SIZE); - s->gen_next_op_idx =3D oi + 1; - - new_op =3D &s->gen_op_buf[oi]; - *new_op =3D (TCGOp){ - .opc =3D opc, - .prev =3D prev, - .next =3D next - }; - s->gen_op_buf[next].prev =3D oi; - old_op->next =3D oi; - + TCGOp *new_op =3D tcg_op_alloc(opc); + QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); return new_op; } =20 @@ -2006,23 +1978,19 @@ static void tcg_la_bb_end(TCGContext *s) static void liveness_pass_1(TCGContext *s) { int nb_globals =3D s->nb_globals; - int oi, oi_prev; + TCGOp *op, *op_prev; =20 tcg_la_func_end(s); =20 - for (oi =3D s->gen_op_buf[0].prev; oi !=3D 0; oi =3D oi_prev) { + QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) { int i, nb_iargs, nb_oargs; TCGOpcode opc_new, opc_new2; bool have_opc_new2; TCGLifeData arg_life =3D 0; TCGTemp *arg_ts; - - TCGOp * const op =3D &s->gen_op_buf[oi]; TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; =20 - oi_prev =3D op->prev; - switch (opc) { case INDEX_op_call: { @@ -2233,8 +2201,9 @@ static void liveness_pass_1(TCGContext *s) static bool liveness_pass_2(TCGContext *s) { int nb_globals =3D s->nb_globals; - int nb_temps, i, oi, oi_next; + int nb_temps, i; bool changes =3D false; + TCGOp *op, *op_next; =20 /* Create a temporary for each indirect global. */ for (i =3D 0; i < nb_globals; ++i) { @@ -2256,16 +2225,13 @@ static bool liveness_pass_2(TCGContext *s) its->state =3D TS_DEAD; } =20 - for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { - TCGOp *op =3D &s->gen_op_buf[oi]; + QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { TCGOpcode opc =3D op->opc; const TCGOpDef *def =3D &tcg_op_defs[opc]; TCGLifeData arg_life =3D op->life; int nb_iargs, nb_oargs, call_flags; TCGTemp *arg_ts, *dir_ts; =20 - oi_next =3D op->next; - if (opc =3D=3D INDEX_op_call) { nb_oargs =3D op->callo; nb_iargs =3D op->calli; @@ -3168,13 +3134,16 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) #ifdef CONFIG_PROFILER TCGProfile *prof =3D &s->prof; #endif - int i, oi, oi_next, num_insns; + int i, num_insns; + TCGOp *op; =20 #ifdef CONFIG_PROFILER { int n; =20 - n =3D s->gen_op_buf[0].prev + 1; + QTAILQ_FOREACH(op, &s->ops, link) { + n++; + } atomic_set(&prof->op_count, prof->op_count + n); if (n > prof->op_count_max) { atomic_set(&prof->op_count_max, n); @@ -3260,11 +3229,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 num_insns =3D -1; - for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { - TCGOp * const op =3D &s->gen_op_buf[oi]; + QTAILQ_FOREACH(op, &s->ops, link) { TCGOpcode opc =3D op->opc; =20 - oi_next =3D op->next; #ifdef CONFIG_PROFILER atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] += 1); #endif --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513357790624287.8974788852522; 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[141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=T0qZ0yQVuTEP92yeIk5MiIxes6YEX/ZnuZg0aGwqsdM=; b=bfCS0lnnlHxxM+Hxd3xdUubeEQOM/goTrlEelwO640rQIaVED9Ymu2vdF7Axt7eDDW uBOKYuhIYwLKmgut1rxV8TxW4f6qkfVGrT90dA0ohR4p0BZg+R2ith1anFeONCl1qWMq vzNViZdel8St7T2YiWzQed9NQ3FTvVSeGfey8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=T0qZ0yQVuTEP92yeIk5MiIxes6YEX/ZnuZg0aGwqsdM=; b=OlNm+Kf2FyL0cNcgerEQFGRHtX4nla5Kwghkhe6inWiGKQkdG6bNQopMU1pBDSa7LA RAc7CeB7aYmO1Yr8eGGXB/MWQD4yUWRtlrRKiPU0xbqO8tYcbVK3D3BnoZy1v/fGyiZz +YioMcOMRWhOE4lFPh5R/lT2blIdQS5VD9RFV0KdRXHejWneuMl7kuaqjLBRJTbfSNLH ud3uVnwGJILN6hfnIvM4RfvCvObbYoPLfdq6L3N1u1R34SCYTJuQxiBa5SFO9eUPhKOL FO50xKS5rBlEY9nBd073ArIscJ7SNh/Yc06jyMQYHinOau4cn/kReIv5Y93hdnlyL43f ruIA== X-Gm-Message-State: AKGB3mIFiSs1KQ4Iiw2XlHfzZkYFlM3+bQfeJ1ZBhSAqUUWZNpouoXeh CPii+3T3+bBn8nFVt0/ziFxr/VodD1A= X-Google-Smtp-Source: ACJfBotxxnqZZPSliSk7eN9xQzotkugDrFvsaoE+9GUSFwmilEBhged2N1qyCYKUD9fDPm1j1uJP9w== X-Received: by 10.107.173.223 with SMTP id m92mr13749824ioo.28.1513357665222; Fri, 15 Dec 2017 09:07:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:30 -0600 Message-Id: <20171215170732.31125-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 5/7] tcg: Generalize TCGOp parameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We had two fields specific to INDEX_op_call. Rename these and add some macros so that the fields may be reused for other opcodes. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.h | 10 ++++++---- tcg/optimize.c | 4 ++-- tcg/tcg.c | 22 +++++++++++----------- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index a577447846..f25efa9795 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -566,10 +566,9 @@ typedef uint16_t TCGLifeData; typedef struct TCGOp { TCGOpcode opc : 8; /* 8 */ =20 - /* The number of out and in parameter for a call. */ - unsigned calli : 4; /* 12 */ - unsigned callo : 2; /* 14 */ - unsigned : 2; /* 16 */ + /* Parameters for this opcode. See below. */ + unsigned param1 : 4; /* 12 */ + unsigned param2 : 4; /* 16 */ =20 /* Lifetime data of the operands. */ unsigned life : 16; /* 32 */ @@ -581,6 +580,9 @@ typedef struct TCGOp { TCGArg args[MAX_OPC_PARAM]; } TCGOp; =20 +#define TCGOP_CALLI(X) (X)->param1 +#define TCGOP_CALLO(X) (X)->param2 + /* Make sure operands fit in the bitfields above. */ QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); =20 diff --git a/tcg/optimize.c b/tcg/optimize.c index e495680e95..2cbbeefd53 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -627,8 +627,8 @@ void tcg_optimize(TCGContext *s) /* Count the arguments, and initialize the temps that are going to be used */ if (opc =3D=3D INDEX_op_call) { - nb_oargs =3D op->callo; - nb_iargs =3D op->calli; + nb_oargs =3D TCGOP_CALLO(op); + nb_iargs =3D TCGOP_CALLI(op); for (i =3D 0; i < nb_oargs + nb_iargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); if (ts) { diff --git a/tcg/tcg.c b/tcg/tcg.c index f26949a900..93caa0be93 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1430,7 +1430,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) } else { nb_rets =3D 0; } - op->callo =3D nb_rets; + TCGOP_CALLO(op) =3D nb_rets; =20 real_args =3D 0; for (i =3D 0; i < nargs; i++) { @@ -1469,10 +1469,10 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) } op->args[pi++] =3D (uintptr_t)func; op->args[pi++] =3D flags; - op->calli =3D real_args; + TCGOP_CALLI(op) =3D real_args; =20 /* Make sure the fields didn't overflow. */ - tcg_debug_assert(op->calli =3D=3D real_args); + tcg_debug_assert(TCGOP_CALLI(op) =3D=3D real_args); tcg_debug_assert(pi <=3D ARRAY_SIZE(op->args)); =20 #if defined(__sparc__) && !defined(__arch64__) \ @@ -1634,8 +1634,8 @@ void tcg_dump_ops(TCGContext *s) } } else if (c =3D=3D INDEX_op_call) { /* variable number of arguments */ - nb_oargs =3D op->callo; - nb_iargs =3D op->calli; + nb_oargs =3D TCGOP_CALLO(op); + nb_iargs =3D TCGOP_CALLI(op); nb_cargs =3D def->nb_cargs; =20 /* function name, flags, out args */ @@ -1996,8 +1996,8 @@ static void liveness_pass_1(TCGContext *s) { int call_flags; =20 - nb_oargs =3D op->callo; - nb_iargs =3D op->calli; + nb_oargs =3D TCGOP_CALLO(op); + nb_iargs =3D TCGOP_CALLI(op); call_flags =3D op->args[nb_oargs + nb_iargs + 1]; =20 /* pure functions can be removed if their result is unused= */ @@ -2233,8 +2233,8 @@ static bool liveness_pass_2(TCGContext *s) TCGTemp *arg_ts, *dir_ts; =20 if (opc =3D=3D INDEX_op_call) { - nb_oargs =3D op->callo; - nb_iargs =3D op->calli; + nb_oargs =3D TCGOP_CALLO(op); + nb_iargs =3D TCGOP_CALLI(op); call_flags =3D op->args[nb_oargs + nb_iargs + 1]; } else { nb_iargs =3D def->nb_iargs; @@ -2915,8 +2915,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) =20 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { - const int nb_oargs =3D op->callo; - const int nb_iargs =3D op->calli; + const int nb_oargs =3D TCGOP_CALLO(op); + const int nb_iargs =3D TCGOP_CALLI(op); const TCGLifeData arg_life =3D op->life; int flags, nb_regs, i; TCGReg reg; --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513358071599143.55731490576784; Fri, 15 Dec 2017 09:14:31 -0800 (PST) Received: from localhost ([::1]:47810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtYu-0006Zv-3w for importer@patchew.org; Fri, 15 Dec 2017 12:14:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtSg-0001XX-LF for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePtSd-0002z2-Kn for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:50 -0500 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:40225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ePtSd-0002yY-Et for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:47 -0500 Received: by mail-it0-x241.google.com with SMTP id f190so20452322ita.5 for ; Fri, 15 Dec 2017 09:07:47 -0800 (PST) Received: from cloudburst.twiddle.net (141-126-166-226.dhcp.chtrptr.net. [141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=/YlH32H9tYHZq9RETQ643K/J2do610JFBVn7ZN+NgVA=; b=JG3umnsS1VPan+LvmyTa81SQYZJg9++Lhx7gLH/eWPcO525nm7urMMmRxIjI6CYAXG yeyB7+LQ1FpclN1jGUpYTGM+P0QqmwpFs/xpO79Eq3nt034hE1wnFP7sgkgb9fhURAZd lI/BGBG5Qn8sRYMhoHpM53Ug/097jALQ7qxEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/YlH32H9tYHZq9RETQ643K/J2do610JFBVn7ZN+NgVA=; b=DaFw3w8jRJxPrT5Gk6DZfzhVmaSyS4lBDCOxO4DDbHfyiayJnVgnjJhIV6WSeP+0Ek y3IrRaV1+VGJlRu8tgGoi0RC2o4nd3miraeTXBAUFUgGsVIqSoYYKo8Z/8ORMxVvGlmJ T/uOvLn7GmFOQM+KTQDFwd4c6ycp/1IF+VoenC4w+Wf3i5ER1wa42tvp/1GGJohr0Wfw JEkxef4i+Y7Mk9PF7lcjKnfFmSeINgvSq/WMCs9S1x+NkzSOj7uAsUXyp8dCaskyd47S 9mgnQe9fO1Z5Ly2vXRByF06Go6p5g0lNaraaQr8IfImCA5Kl5Nn34dIynvT4Q83HEUVm leDA== X-Gm-Message-State: AKGB3mIZ5ImELyINVGsrrPuQqkMiQ7yiTwrzn4VFbAdfWw0bKtk6f0Lh 3eH7iZKduVgTaCDWaKOG79tX7j59FtU= X-Google-Smtp-Source: ACJfBosmkOx8R8GfFejVq4Od+K6L/pXaYf50eFYG8x1UU5yt4higwc1qN36hHnIF4m1l8mFMhA9bPA== X-Received: by 10.36.206.130 with SMTP id v124mr8925704itg.81.1513357666676; Fri, 15 Dec 2017 09:07:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:31 -0600 Message-Id: <20171215170732.31125-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 6/7] tcg: Add tcg_signed_cond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Complimenting the existing tcg_unsigned_cond. Signed-off-by: Richard Henderson --- tcg/tcg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/tcg.h b/tcg/tcg.h index f25efa9795..8c45f7edbc 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -488,6 +488,12 @@ static inline TCGCond tcg_unsigned_cond(TCGCond c) return c & 2 ? (TCGCond)(c ^ 6) : c; } =20 +/* Create a "signed" version of an "unsigned" comparison. */ +static inline TCGCond tcg_signed_cond(TCGCond c) +{ + return c & 4 ? (TCGCond)(c ^ 6) : c; +} + /* Must a comparison be considered unsigned? */ static inline bool is_unsigned_cond(TCGCond c) { --=20 2.14.3 From nobody Tue Oct 28 14:38:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1513358174202313.1169023787247; Fri, 15 Dec 2017 09:16:14 -0800 (PST) Received: from localhost ([::1]:47826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtai-0008Ae-Lg for importer@patchew.org; Fri, 15 Dec 2017 12:16:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePtSh-0001Xt-1N for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePtSf-00030b-IY for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:50 -0500 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:46710) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ePtSf-00030F-Bw for qemu-devel@nongnu.org; Fri, 15 Dec 2017 12:07:49 -0500 Received: by mail-it0-x241.google.com with SMTP id t1so21005784ite.5 for ; Fri, 15 Dec 2017 09:07:49 -0800 (PST) Received: from cloudburst.twiddle.net (141-126-166-226.dhcp.chtrptr.net. [141.126.166.226]) by smtp.gmail.com with ESMTPSA id k23sm4012974iti.22.2017.12.15.09.07.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Dec 2017 09:07:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=aPq274UtH5AOezSBTd02y6GjFpANpcFMJXYRZgQkE9M=; b=DYY91lQ/FDMzg5t6QCz07HKrrOnhqMYDUHSUmn4gCih3g63Vu4o2Hmvcepx5B2VlS0 Cbe9y24fmOTVdAQq16/vYKI8W6dk6oBZLcKW93lPpLhwq0ditGomhLUxU30dH6tUzXTA 2GWe0US11GctGK4pD8sAxjIVebguMPEEEMzFg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=aPq274UtH5AOezSBTd02y6GjFpANpcFMJXYRZgQkE9M=; b=QkxYSbfoqI6biqx/FovuGomL30UrsJc3arm/ixmGrY/0XQ/RizCuw1Xzp0NmvumT/J KltT8KK04zY9Wtbobj2VzGfRM6GiHBqRwI3QRw9DZGRZ+x3YIPv7xwuEbKtJsTjDCm8R W3pX+KLDMf5IipoEM1g3LtkhekDDGRa+PgNJVkqw7yMr+jcxjICdvrhaw0YbbPru5LDl +tWEUN1F4QXwl3ymq4rJJ0w0GGMYWPZPZnXpp581rtTtZcVvHBlhhXSlC2+668kosgfm ASPqMlJYrQfdhyUw7JepR5dkEkvUFfENgqOg0OdBIpN2UqWyZl5oKTaxx70hil3eG7b0 VLZA== X-Gm-Message-State: AKGB3mI+QJ1qXDgQ+6TYavwSw1hGquCmQ9EO8PLwNVrGEUXrnAzvv47j U2o5blPLUMTdCnHQ+VUGfU2ztn1fvNs= X-Google-Smtp-Source: ACJfBoshFYnDTEUD1L5Am48yeBmmNVOvPe8cACC2brm5/gErXwUhYk2P2EAPMSIhRtNpEPjiJxpu3g== X-Received: by 10.107.53.86 with SMTP id c83mr12324628ioa.41.1513357668464; Fri, 15 Dec 2017 09:07:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Dec 2017 11:07:32 -0600 Message-Id: <20171215170732.31125-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171215170732.31125-1-richard.henderson@linaro.org> References: <20171215170732.31125-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 7/7] tcg: Allow 6 arguments to TCG helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We already handle this in the backends, and the lifetime datum for the TCGOp is already large enough. Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 11 +++++++++++ include/exec/helper-head.h | 2 ++ include/exec/helper-proto.h | 5 +++++ include/exec/helper-tcg.h | 7 +++++++ tcg/tcg.h | 2 +- tcg/tci.c | 12 ++++++++---- tcg/tci/tcg-target.inc.c | 6 ++++-- 7 files changed, 38 insertions(+), 7 deletions(-) diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 15204ab961..22381a1708 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -56,6 +56,16 @@ static inline void glue(gen_helper_, name)(dh_retvar_dec= l(ret) \ tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ } =20 +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ +{ \ + TCGTemp *args[6] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ +} + #include "helper.h" #include "trace/generated-helpers.h" #include "trace/generated-helpers-wrappers.h" @@ -67,6 +77,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 #undef GEN_HELPER =20 #endif /* HELPER_GEN_H */ diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 639eefdbc0..e1fd08f2ba 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -125,6 +125,8 @@ DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \ DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) +#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \ + DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) =20 /* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_= n. */ =20 diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 954bef85ce..74943edb13 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -26,6 +26,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), = dh_ctype(t3), \ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ dh_ctype(t4), dh_ctype(t5)); =20 +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), dh_ctype(t6)); + #include "helper.h" #include "trace/generated-helpers.h" #include "tcg-runtime.h" @@ -36,5 +40,6 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), d= h_ctype(t3), \ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 =20 #endif /* HELPER_PROTO_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index b0c5bafa99..b3bdb0c399 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -39,6 +39,12 @@ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, =20 +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + { .func =3D HELPER(NAME), .name =3D str(NAME), .flags =3D FLAGS, \ + .sizemask =3D dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ + | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, + #include "helper.h" #include "trace/generated-helpers.h" #include "tcg-runtime.h" @@ -50,5 +56,6 @@ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 =20 #endif /* HELPER_TCG_H */ diff --git a/tcg/tcg.h b/tcg/tcg.h index 8c45f7edbc..2ce497cebf 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -41,7 +41,7 @@ #else #define MAX_OPC_PARAM_PER_ARG 1 #endif -#define MAX_OPC_PARAM_IARGS 5 +#define MAX_OPC_PARAM_IARGS 6 #define MAX_OPC_PARAM_OARGS 1 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) =20 diff --git a/tcg/tci.c b/tcg/tci.c index 63f2cd54ab..33edca1903 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -40,11 +40,12 @@ tcg_abort(); \ } while (0) =20 -#if MAX_OPC_PARAM_IARGS !=3D 5 +#if MAX_OPC_PARAM_IARGS !=3D 6 # error Fix needed, number of supported input arguments changed! #endif #if TCG_TARGET_REG_BITS =3D=3D 32 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, + tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, @@ -52,7 +53,7 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg= _target_ulong, #else typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong); + tcg_target_ulong, tcg_target_ulong); #endif =20 static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) @@ -520,7 +521,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *= tb_ptr) tci_read_reg(regs, TCG_REG_R7), tci_read_reg(regs, TCG_REG_R8), tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10)); + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11), + tci_read_reg(regs, TCG_REG_R12)); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else @@ -528,7 +531,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *= tb_ptr) tci_read_reg(regs, TCG_REG_R1), tci_read_reg(regs, TCG_REG_R2), tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R5)); + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 913c3802a3..cc949bea85 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -292,7 +292,7 @@ static const int tcg_target_reg_alloc_order[] =3D { #endif }; =20 -#if MAX_OPC_PARAM_IARGS !=3D 5 +#if MAX_OPC_PARAM_IARGS !=3D 6 # error Fix needed, number of supported input arguments changed! #endif =20 @@ -305,14 +305,16 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R4, #endif TCG_REG_R5, + TCG_REG_R6, #if TCG_TARGET_REG_BITS =3D=3D 32 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ - TCG_REG_R6, TCG_REG_R7, #if TCG_TARGET_NB_REGS >=3D 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R12, #else # error Too few input registers available #endif --=20 2.14.3