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Iglesias" , Peter Maydell , Michael Walle , Andrzej Zaborowski , Andrew Baumann , Andrey Smirnov , Andrey Yurovsky Date: Fri, 15 Dec 2017 00:15:39 -0300 Message-Id: <20171215031547.31006-13-f4bug@amsat.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171215031547.31006-1-f4bug@amsat.org> References: <20171215031547.31006-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v2 12/20] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Prasad J Pandit , Peter Crosthwaite , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Sai Pavan Boddu , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 running qtests: $ make check-qtest-arm GTESTER check-qtest-arm SDHC rd_4b @0x44 not implemented SDHC wr_4b @0x40 <- 0x89abcdef not implemented SDHC wr_4b @0x44 <- 0x01234567 not implemented Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/sd/sdhci.h | 4 ++-- hw/sd/sdhci.c | 23 +++++++++++++++++++---- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 715048d77b..a8ffac9dba 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -76,8 +76,8 @@ typedef struct SDHCIState { uint16_t acmd12errsts; /* Auto CMD12 error status register */ uint64_t admasysaddr; /* ADMA System Address Register */ =20 - uint32_t capareg; /* Capabilities Register */ - uint32_t maxcurr; /* Maximum Current Capabilities Register */ + uint64_t capareg; /* Capabilities Register */ + uint64_t maxcurr; /* Maximum Current Capabilities Register */ uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ uint32_t buf_maxsz; uint16_t data_count; /* current element in FIFO buffer */ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 0f3ff657cf..9c1b28d9dd 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -906,10 +906,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offse= t, unsigned size) ret =3D s->acmd12errsts; break; case SDHC_CAPAREG: - ret =3D s->capareg; + ret =3D (uint32_t)s->capareg; + break; + case SDHC_CAPAREG + 4: + ret =3D (uint32_t)(s->capareg >> 32); break; case SDHC_MAXCURR: - ret =3D s->maxcurr; + ret =3D (uint32_t)s->maxcurr; + break; + case SDHC_MAXCURR + 4: + ret =3D (uint32_t)(s->maxcurr >> 32); break; case SDHC_ADMAERR: ret =3D s->admaerr; @@ -1129,6 +1135,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) } sdhci_update_irq(s); break; + + case SDHC_CAPAREG: + case SDHC_CAPAREG + 4: + case SDHC_MAXCURR: + case SDHC_MAXCURR + 4: + qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx + " <- 0x%08x read-only\n", size, offset, value >> shi= ft); + break; + default: qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%= 08x " "not implemented\n", size, offset, value >> shift); @@ -1272,9 +1287,9 @@ const VMStateDescription sdhci_vmstate =3D { /* Capabilities registers provide information on supported features of this * specific host controller implementation */ static Property sdhci_properties[] =3D { - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, + DEFINE_PROP_UINT64("capareg", SDHCIState, capareg, SDHC_CAPAB_REG_DEFAULT), - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), + DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0), DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_qu= irk, false), DEFINE_PROP_LINK("dma-memory", SDHCIState, dma_mr, --=20 2.15.1