From nobody Mon Feb 9 23:43:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512888058296757.6336032663601; Sat, 9 Dec 2017 22:40:58 -0800 (PST) Received: from localhost ([::1]:43628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNvI4-0003aS-H2 for importer@patchew.org; Sun, 10 Dec 2017 01:40:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNvFx-00026Y-V7 for qemu-devel@nongnu.org; Sun, 10 Dec 2017 01:38:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eNvFw-0005zx-9R for qemu-devel@nongnu.org; Sun, 10 Dec 2017 01:38:33 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41858) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eNvFw-0005zW-1C for qemu-devel@nongnu.org; Sun, 10 Dec 2017 01:38:32 -0500 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3852D81DFE for ; Sun, 10 Dec 2017 06:38:31 +0000 (UTC) Received: from xz-mi.redhat.com (ovpn-12-22.pek2.redhat.com [10.72.12.22]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3D7D65DA7A; Sun, 10 Dec 2017 06:38:28 +0000 (UTC) From: Peter Xu To: qemu-devel@nongnu.org Date: Sun, 10 Dec 2017 14:38:15 +0800 Message-Id: <20171210063819.14892-2-peterx@redhat.com> In-Reply-To: <20171210063819.14892-1-peterx@redhat.com> References: <20171210063819.14892-1-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Sun, 10 Dec 2017 06:38:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 1/5] i8259: convert DPRINTFs into trace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , peterx@redhat.com, "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" One thing to mention is that in pic_set_irq() I need to uncomment a few lines in the macros to make sure IRQ value calculation is correct. Signed-off-by: Peter Xu Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/i8259.c | 26 +++++++++++--------------- hw/intc/trace-events | 7 +++++++ 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index fe9ecd6bd4..f12e0b27f1 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -30,17 +30,11 @@ #include "qemu/log.h" #include "hw/isa/i8259_internal.h" #include "hw/intc/intc.h" +#include "trace.h" =20 /* debug PIC */ //#define DEBUG_PIC =20 -#ifdef DEBUG_PIC -#define DPRINTF(fmt, ...) \ - do { printf("pic: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) -#endif - //#define DEBUG_IRQ_LATENCY //#define DEBUG_IRQ_COUNT =20 @@ -122,8 +116,7 @@ static void pic_update_irq(PICCommonState *s) =20 irq =3D pic_get_irq(s); if (irq >=3D 0) { - DPRINTF("pic%d: imr=3D%x irr=3D%x padd=3D%d\n", - s->master ? 0 : 1, s->imr, s->irr, s->priority_add); + trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); qemu_irq_raise(s->int_out[0]); } else { qemu_irq_lower(s->int_out[0]); @@ -140,9 +133,11 @@ static void pic_set_irq(void *opaque, int irq, int lev= el) defined(DEBUG_IRQ_LATENCY) int irq_index =3D s->master ? irq : irq + 8; #endif + + trace_pic_set_irq(s->master, irq, level); + #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) if (level !=3D irq_level[irq_index]) { - DPRINTF("pic_set_irq: irq=3D%d level=3D%d\n", irq_index, level); irq_level[irq_index] =3D level; #ifdef DEBUG_IRQ_COUNT if (level =3D=3D 1) { @@ -223,18 +218,18 @@ int pic_read_irq(DeviceState *d) intno =3D s->irq_base + irq; } =20 -#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY) if (irq =3D=3D 2) { irq =3D irq2 + 8; } -#endif + #ifdef DEBUG_IRQ_LATENCY printf("IRQ%d latency=3D%0.3fus\n", irq, (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND); #endif - DPRINTF("pic_interrupt: irq=3D%d\n", irq); + + trace_pic_interrupt(irq, intno); return intno; } =20 @@ -289,7 +284,8 @@ static void pic_ioport_write(void *opaque, hwaddr addr6= 4, uint32_t val =3D val64; int priority, cmd, irq; =20 - DPRINTF("write: addr=3D0x%02x val=3D0x%02x\n", addr, val); + trace_pic_ioport_write(s->master, addr, val); + if (addr =3D=3D 0) { if (val & 0x10) { pic_init_reset(s); @@ -402,7 +398,7 @@ static uint64_t pic_ioport_read(void *opaque, hwaddr ad= dr, ret =3D s->imr; } } - DPRINTF("read: addr=3D0x%02" HWADDR_PRIx " val=3D0x%02x\n", addr, ret); + trace_pic_ioport_read(s->master, addr, ret); return ret; } =20 diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b298fac7c6..c72b37c5cf 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -1,5 +1,12 @@ # See docs/devel/tracing.txt for syntax documentation. =20 +# hw/intc/i8259.c +pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) "maste= r %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 +pic_set_irq(bool master, int irq, int level) "master %d irq %d level %d" +pic_interrupt(int irq, int intno) "irq %d intno %d" +pic_ioport_write(bool master, uint64_t addr, uint64_t val) "master %d addr= 0x%"PRIx64" val 0x%"PRIx64 +pic_ioport_read(bool master, uint64_t addr, int val) "master %d addr 0x%"P= RIx64" val 0x%x" + # hw/intc/apic_common.c cpu_set_apic_base(uint64_t val) "0x%016"PRIx64 cpu_get_apic_base(uint64_t val) "0x%016"PRIx64 --=20 2.14.3