From nobody Sat Feb 7 08:28:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512660842096945.6276129564621; Thu, 7 Dec 2017 07:34:02 -0800 (PST) Received: from localhost ([::1]:32873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMyBP-0001Ht-GH for importer@patchew.org; Thu, 07 Dec 2017 10:33:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eMy9X-00007a-1Z for qemu-devel@nongnu.org; Thu, 07 Dec 2017 10:32:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eMy9U-0002EK-AT for qemu-devel@nongnu.org; Thu, 07 Dec 2017 10:31:59 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49408) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eMy9U-00029n-1u; Thu, 07 Dec 2017 10:31:56 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B9FFFC04AC48; Thu, 7 Dec 2017 15:31:50 +0000 (UTC) Received: from t460s.redhat.com (ovpn-116-108.ams2.redhat.com [10.36.116.108]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5637D703A5; Thu, 7 Dec 2017 15:31:44 +0000 (UTC) From: David Hildenbrand To: qemu-s390x@nongnu.org, qemu-devel@nongnu.org Date: Thu, 7 Dec 2017 16:31:37 +0100 Message-Id: <20171207153141.15523-2-david@redhat.com> In-Reply-To: <20171207153141.15523-1-david@redhat.com> References: <20171207153141.15523-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Thu, 07 Dec 2017 15:31:50 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 for-2.12 1/5] s390x/kvm: factor out build_channel_report_mcic() into cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , Cornelia Huck , David Hildenbrand , Alexander Graf , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We'll need it later on in two places. Refactor it to just indicate the validity bits. While at it, introduce a define for the used CR14 bit (we'll also need later on). Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 22 ++++++++++++++++++++++ target/s390x/kvm.c | 25 ++----------------------- 2 files changed, 24 insertions(+), 23 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 9cfbbbac04..f29f4ccd8b 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -351,6 +351,9 @@ extern const struct VMStateDescription vmstate_s390_cpu; #define CR0_CPU_TIMER_SC 0x0000000000000400ULL #define CR0_SERVICE_SC 0x0000000000000200ULL =20 +/* Control register 14 bits */ +#define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL + /* MMU */ #define MMU_PRIMARY_IDX 0 #define MMU_SECONDARY_IDX 1 @@ -674,6 +677,25 @@ struct sysib_322 { #define MCIC_VB_CT 0x0000000000020000ULL #define MCIC_VB_CC 0x0000000000010000ULL =20 +static inline uint64_t s390_build_validity_mcic(void) +{ + uint64_t mcic; + + /* Indicate all validity bits (no damage) only. Other bits have to be + * added by the caller. (storage errors, subclasses and subclass modif= iers) + */ + mcic =3D MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_F= P | + MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | + MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; + if (s390_has_feat(S390_FEAT_VECTOR)) { + mcic |=3D MCIC_VB_VR; + } + if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { + mcic |=3D MCIC_VB_GS; + } + return mcic; +} + =20 /* cpu.c */ int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low); diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c index 97c45d5537..9b8b59f2a2 100644 --- a/target/s390x/kvm.c +++ b/target/s390x/kvm.c @@ -1852,33 +1852,12 @@ void kvm_s390_io_interrupt(uint16_t subchannel_id, kvm_s390_floating_interrupt(&irq); } =20 -static uint64_t build_channel_report_mcic(void) -{ - uint64_t mcic; - - /* subclass: indicate channel report pending */ - mcic =3D MCIC_SC_CP | - /* subclass modifiers: none */ - /* storage errors: none */ - /* validity bits: no damage */ - MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | - MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | - MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; - if (s390_has_feat(S390_FEAT_VECTOR)) { - mcic |=3D MCIC_VB_VR; - } - if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { - mcic |=3D MCIC_VB_GS; - } - return mcic; -} - void kvm_s390_crw_mchk(void) { struct kvm_s390_irq irq =3D { .type =3D KVM_S390_MCHK, - .u.mchk.cr14 =3D 1 << 28, - .u.mchk.mcic =3D build_channel_report_mcic(), + .u.mchk.cr14 =3D CR14_CHANNEL_REPORT_SC, + .u.mchk.mcic =3D s390_build_validity_mcic() | MCIC_SC_CP, }; kvm_s390_floating_interrupt(&irq); } --=20 2.14.3