From nobody Tue Feb 10 13:16:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511156666701695.4717320271147; Sun, 19 Nov 2017 21:44:26 -0800 (PST) Received: from localhost ([::1]:55507 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGesQ-0001fz-4K for importer@patchew.org; Mon, 20 Nov 2017 00:44:14 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60639) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGer5-00010y-BT for qemu-devel@nongnu.org; Mon, 20 Nov 2017 00:42:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGer4-0004Aa-4e for qemu-devel@nongnu.org; Mon, 20 Nov 2017 00:42:51 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:59673) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGer3-00049y-Bm; Mon, 20 Nov 2017 00:42:50 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3ygHg7099Mz9s5L; Mon, 20 Nov 2017 16:42:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1511156563; bh=1lylH/on20hmXhVAbPPhn0jhBPKE0hVw6z5GDs+USxE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o6xtjwGMMKYgdOEomFX7HLC033kxbZa6II5vvZ0fWSzLN4cbvSyScDowfe+hgjCLp gFuiZwIbFNBmS4bqE94wIItc5PUagYW3Hpl4y4EGLkUc3KQxiPUZJ+TY1zLJo1Wh2e gm0p0gRx1iYi/+GNC0mvQGkyTSaGpvJUC0TtDR4E= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 20 Nov 2017 16:42:38 +1100 Message-Id: <20171120054239.8739-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171120054239.8739-1-david@gibson.dropbear.id.au> References: <20171120054239.8739-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 1/2] target/ppc: Update setting of cpu features to account for compat modes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, agraf@suse.de, groug@kaod.org, qemu-ppc@nongnu.org, Suraj Jitindar Singh , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Suraj Jitindar Singh The device tree nodes ibm,arch-vec-5-platform-support and ibm,pa-features are used to communicate features of the cpu to the guest operating system. The properties of each of these are determined based on the selected cpu model and the availability of hypervisor features. Currently the compatibility mode of the cpu is not taken into account. The ibm,arch-vec-5-platform-support node is used to communicate the level of support for various ISAv3 processor features to the guest before CAS to inform the guests' request. The available mmu mode should only be hash unless the cpu is a POWER9 which is not in a prePOWER9 compat mode, in which case the available modes depend on the accelerator and the hypervisor capabilities. The ibm,pa-featues node is used to communicate the level of cpu support for various features to the guest os. This should only contain features relevant to the operating mode of the processor, that is the selected cpu model taking into account any compat mode. This means that the compat mode should be taken into account when choosing the properties of ibm,pa-features and they should match the compat mode selected, or the cpu model selected if no compat mode. Update the setting of these cpu features in the device tree as described above to properly take into account any compat mode. We use the ppc_check_compat function which takes into account the current processor model and the cpu compat mode. Signed-off-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- hw/ppc/spapr.c | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d682f013d4..6841bd294b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -44,6 +44,7 @@ #include "migration/register.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" +#include "cpu-models.h" #include "qom/cpu.h" =20 #include "hw/boards.h" @@ -252,9 +253,10 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offs= et, PowerPCCPU *cpu) } =20 /* Populate the "ibm,pa-features" property */ -static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int of= fset, - bool legacy_guest) +static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int off= set, + bool legacy_guest) { + CPUPPCState *env =3D &cpu->env; uint8_t pa_features_206[] =3D { 6, 0, 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; uint8_t pa_features_207[] =3D { 24, 0, @@ -287,23 +289,22 @@ static void spapr_populate_pa_features(CPUPPCState *e= nv, void *fdt, int offset, /* 60: NM atomic, 62: RNG */ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ }; - uint8_t *pa_features; + uint8_t *pa_features =3D NULL; size_t pa_size; =20 - switch (POWERPC_MMU_VER(env->mmu_model)) { - case POWERPC_MMU_VER_2_06: + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr= )) { pa_features =3D pa_features_206; pa_size =3D sizeof(pa_features_206); - break; - case POWERPC_MMU_VER_2_07: + } + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr= )) { pa_features =3D pa_features_207; pa_size =3D sizeof(pa_features_207); - break; - case POWERPC_MMU_VER_3_00: + } + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr= )) { pa_features =3D pa_features_300; pa_size =3D sizeof(pa_features_300); - break; - default: + } + if (!pa_features) { return; } =20 @@ -340,7 +341,6 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) =20 CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; DeviceClass *dc =3D DEVICE_GET_CLASS(cs); int index =3D spapr_vcpu_id(cpu); int compat_smt =3D MIN(smp_threads, ppc_compat_max_threads(cpu)); @@ -384,7 +384,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineSt= ate *spapr) return ret; } =20 - spapr_populate_pa_features(env, fdt, offset, + spapr_populate_pa_features(cpu, fdt, offset, spapr->cas_legacy_guest_workaroun= d); } return ret; @@ -579,7 +579,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, page_sizes_prop, page_sizes_prop_size))); } =20 - spapr_populate_pa_features(env, fdt, offset, false); + spapr_populate_pa_features(cpu, fdt, offset, false); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); @@ -949,7 +949,11 @@ static void spapr_dt_ov5_platform_support(void *fdt, i= nt chosen) 26, 0x40, /* Radix options: GTSE =3D=3D yes. */ }; =20 - if (kvm_enabled()) { + if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, + first_ppc_cpu->compat_pvr)) { + /* If we're in a pre POWER9 compat mode then the guest should do h= ash */ + val[3] =3D 0x00; /* Hash */ + } else if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { val[3] =3D 0x80; /* OV5_MMU_BOTH */ } else if (kvmppc_has_cap_mmu_radix()) { @@ -958,13 +962,8 @@ static void spapr_dt_ov5_platform_support(void *fdt, i= nt chosen) val[3] =3D 0x00; /* Hash */ } } else { - if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { - /* V3 MMU supports both hash and radix (with dynamic switching= ) */ - val[3] =3D 0xC0; - } else { - /* Otherwise we can only do hash */ - val[3] =3D 0x00; - } + /* V3 MMU supports both hash and radix in tcg (with dynamic switch= ing) */ + val[3] =3D 0xC0; } _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", val, sizeof(val))); --=20 2.14.3