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Mon, 13 Nov 2017 11:15:04 -0500 X-ASG-Debug-ID: 1510589704-0768e41b31834d50001-jgbH7p X-Barracuda-Envelope-From: Michael.Nawrocki@gtri.gatech.edu From: Mike Nawrocki To: , Date: Mon, 13 Nov 2017 11:14:45 -0500 X-ASG-Orig-Subj: [PATCH v3 1/3] Switch AMD CFI flash to use new MMIO API Message-ID: <20171113161446.2862-2-michael.nawrocki@gtri.gatech.edu> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171113161446.2862-1-michael.nawrocki@gtri.gatech.edu> References: <20171113161446.2862-1-michael.nawrocki@gtri.gatech.edu> MIME-Version: 1.0 X-Originating-IP: [130.207.205.130] X-ClientProxiedBy: apatlisdmfe4.core.gtri.org (10.41.47.104) To tybee.core.gtri.org (10.41.1.49) X-Barracuda-Connect: jekyll.core.gtri.org[10.41.1.48] X-Barracuda-Start-Time: 1510589704 X-Barracuda-Encrypted: ECDHE-RSA-AES128-SHA256 X-Barracuda-URL: https://130.207.199.168:443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at gtri.gatech.edu X-Barracuda-Scan-Msg-Size: 4467 X-Barracuda-BRTS-Status: 1 X-Barracuda-Spam-Score: 0.00 X-Barracuda-Spam-Status: No, SCORE=0.00 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=1000.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.44788 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 130.207.199.168 Subject: [Qemu-devel] [PATCH v3 1/3] Switch AMD CFI flash to use new MMIO API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kwolf@redhat.com, peter.maydell@linaro.org, pbonzini@redhat.com, Mike Nawrocki , mreitz@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Mike Nawrocki --- hw/block/pflash_cfi02.c | 97 +++++++++------------------------------------= ---- 1 file changed, 18 insertions(+), 79 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index c81ddd3a99..a81df913f6 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -138,12 +138,12 @@ static void pflash_timer (void *opaque) pfl->cmd =3D 0; } =20 -static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, - int width, int be) +static uint64_t pflash_read(pflash_t *pfl, hwaddr offset, + int width, int be) { hwaddr boff; - uint32_t ret; uint8_t *p; + uint64_t ret; =20 DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); ret =3D -1; @@ -261,7 +261,7 @@ static void pflash_update(pflash_t *pfl, int offset, } =20 static void pflash_write (pflash_t *pfl, hwaddr offset, - uint32_t value, int width, int be) + uint64_t value, int width, int be) { hwaddr boff; uint8_t *p; @@ -494,102 +494,41 @@ static void pflash_write (pflash_t *pfl, hwaddr offs= et, pfl->cmd =3D 0; } =20 - -static uint32_t pflash_readb_be(void *opaque, hwaddr addr) -{ - return pflash_read(opaque, addr, 1, 1); -} - -static uint32_t pflash_readb_le(void *opaque, hwaddr addr) -{ - return pflash_read(opaque, addr, 1, 0); -} - -static uint32_t pflash_readw_be(void *opaque, hwaddr addr) +static uint64_t pflash_read_le(void *opaque, hwaddr addr, unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 2, 1); + return pflash_read(pfl, addr, size, 0); } =20 -static uint32_t pflash_readw_le(void *opaque, hwaddr addr) +static uint64_t pflash_read_be(void *opaque, hwaddr addr, unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 2, 0); + return pflash_read(pfl, addr, size, 1); } =20 -static uint32_t pflash_readl_be(void *opaque, hwaddr addr) +static void pflash_write_le(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 4, 1); + pflash_write(pfl, addr, data, size, 0); } =20 -static uint32_t pflash_readl_le(void *opaque, hwaddr addr) +static void pflash_write_be(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 4, 0); -} - -static void pflash_writeb_be(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_write(opaque, addr, value, 1, 1); -} - -static void pflash_writeb_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_write(opaque, addr, value, 1, 0); -} - -static void pflash_writew_be(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 2, 1); -} - -static void pflash_writew_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 2, 0); -} - -static void pflash_writel_be(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 4, 1); -} - -static void pflash_writel_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 4, 0); + pflash_write(pfl, addr, data, size, 1); } =20 static const MemoryRegionOps pflash_cfi02_ops_be =3D { - .old_mmio =3D { - .read =3D { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, - .write =3D { pflash_writeb_be, pflash_writew_be, pflash_writel_be,= }, - }, + .read =3D pflash_read_be, + .write =3D pflash_write_be, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 static const MemoryRegionOps pflash_cfi02_ops_le =3D { - .old_mmio =3D { - .read =3D { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, - .write =3D { pflash_writeb_le, pflash_writew_le, pflash_writel_le,= }, - }, + .read =3D pflash_read_le, + .write =3D pflash_write_le, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 --=20 2.14.2