From nobody Thu May 2 07:23:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510345729848604.571623158984; Fri, 10 Nov 2017 12:28:49 -0800 (PST) Received: from localhost ([::1]:43367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eDFus-0008NQ-Sd for importer@patchew.org; Fri, 10 Nov 2017 15:28:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eDFsn-0007HM-OM for qemu-devel@nongnu.org; Fri, 10 Nov 2017 15:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eDFsk-0002U9-GF for qemu-devel@nongnu.org; Fri, 10 Nov 2017 15:26:33 -0500 Received: from relay2.gtri.gatech.edu ([130.207.199.168]:44591) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eDFsk-0002TZ-8x for qemu-devel@nongnu.org; Fri, 10 Nov 2017 15:26:30 -0500 Received: from jekyll.core.gtri.org (jekyll.core.gtri.org [10.41.1.48]) by relay2.gtri.gatech.edu with ESMTP id dy7ROj8RqFW4LPAW (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Fri, 10 Nov 2017 15:26:27 -0500 (EST) Received: from tybee.core.gtri.org (10.41.1.49) by jekyll.core.gtri.org (10.41.1.48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Fri, 10 Nov 2017 15:26:27 -0500 Received: from tia-mxn-d01.ctisl.gtri.org (130.207.205.130) by tybee.core.gtri.org (10.41.1.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Fri, 10 Nov 2017 15:26:26 -0500 X-ASG-Debug-ID: 1510345587-0768e41b2e7f6fb0001-jgbH7p X-Barracuda-Envelope-From: Michael.Nawrocki@gtri.gatech.edu From: Mike Nawrocki To: , Date: Fri, 10 Nov 2017 15:25:56 -0500 X-ASG-Orig-Subj: [PATCH v2 1/1] Add 8-byte access, interleaving to AMD CFI devices Message-ID: <20171110202556.28541-2-michael.nawrocki@gtri.gatech.edu> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171110202556.28541-1-michael.nawrocki@gtri.gatech.edu> References: <20171110202556.28541-1-michael.nawrocki@gtri.gatech.edu> MIME-Version: 1.0 X-Originating-IP: [130.207.205.130] X-ClientProxiedBy: apatlisdmfe4.core.gtri.org (10.41.47.104) To tybee.core.gtri.org (10.41.1.49) X-Barracuda-Connect: jekyll.core.gtri.org[10.41.1.48] X-Barracuda-Start-Time: 1510345587 X-Barracuda-Encrypted: ECDHE-RSA-AES128-SHA256 X-Barracuda-URL: https://130.207.199.168:443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at gtri.gatech.edu X-Barracuda-Scan-Msg-Size: 24920 X-Barracuda-BRTS-Status: 1 X-Barracuda-Spam-Score: 0.50 X-Barracuda-Spam-Status: No, SCORE=0.50 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=1000.0 tests=BSF_RULE7568M X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.44710 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- 0.50 BSF_RULE7568M Custom Rule 7568M X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 130.207.199.168 Subject: [Qemu-devel] [PATCH v2 1/1] Add 8-byte access, interleaving to AMD CFI devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kwolf@redhat.com, peter.maydell@linaro.org, Mike Nawrocki , mreitz@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds 8-byte wide access support to AMD CFI flash devices. Additionally, it migrates the MMIO operations from old_mmio to the new API. Finally, it mirrors the interleaving support already in place in pflash_cfi01.c, using the max_device_width and device_width properties. Signed-off-by: Mike Nawrocki --- hw/block/pflash_cfi02.c | 491 +++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 337 insertions(+), 154 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index c81ddd3a99..1571148f14 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -18,7 +18,7 @@ */ =20 /* - * For now, this code can emulate flashes of 1, 2 or 4 bytes width. + * For now, this code can emulate flashes of 1, 2, 4, or 8 bytes width. * Supported commands/modes are: * - flash read * - flash write @@ -28,11 +28,14 @@ * - unlock bypass command * - CFI queries * - * It does not support flash interleaving. * It does not implement boot blocs with reduced size * It does not implement software data protection as found in many real ch= ips * It does not implement erase suspend/resume commands * It does not implement multiple sectors erase + * + * Flash interleaving is partially supported using the device_width and + * max_device_width properties, as in pflash_cfi01.c + * Issuing commands to individual members of the flash array is not suppor= ted. */ =20 #include "qemu/osdep.h" @@ -40,6 +43,7 @@ #include "hw/block/flash.h" #include "qapi/error.h" #include "qemu/timer.h" +#include "qemu/bitops.h" #include "sysemu/block-backend.h" #include "exec/address-spaces.h" #include "qemu/host-utils.h" @@ -69,7 +73,9 @@ struct pflash_t { uint32_t nb_blocs; uint32_t chip_len; uint8_t mappings; - uint8_t width; + uint8_t bank_width; + uint8_t device_width; /* If 0, device width not specified. */ + uint8_t max_device_width; /* max device width in bytes */ uint8_t be; int wcycle; /* if 0, the flash is read normally */ int bypass; @@ -138,12 +144,190 @@ static void pflash_timer (void *opaque) pfl->cmd =3D 0; } =20 -static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, - int width, int be) +static uint64_t pflash_cfi_query(pflash_t *pfl, hwaddr offset) { + int i; + uint64_t resp =3D 0; hwaddr boff; - uint32_t ret; - uint8_t *p; + + /* Adjust incoming offset to match expected device-width + * addressing. CFI query addresses are always specified in terms of + * the maximum supported width of the device. This means that x8 + * devices and x8/x16 devices in x8 mode behave differently. For + * devices that are not used at their max width, we will be + * provided with addresses that use higher address bits than + * expected (based on the max width), so we will shift them lower + * so that they will match the addresses used when + * device_width=3D=3Dmax_device_width. + */ + boff =3D offset >> (ctz32(pfl->bank_width) + + ctz32(pfl->max_device_width) - ctz32(pfl->device_wid= th)); + + if (boff > pfl->cfi_len) { + return 0; + } + /* Now we will construct the CFI response generated by a single + * device, then replicate that for all devices that make up the + * bus. For wide parts used in x8 mode, CFI query responses + * are different than native byte-wide parts. + */ + resp =3D pfl->cfi_table[boff]; + if (pfl->device_width !=3D pfl->max_device_width) { + /* The only case currently supported is x8 mode for a + * wider part. + */ + if (pfl->device_width !=3D 1 || pfl->bank_width > 8) { + DPRINTF("%s: Unsupported device configuration: " + "device_width=3D%d, max_device_width=3D%d\n", + __func__, pfl->device_width, + pfl->max_device_width); + return 0; + } + /* CFI query data is repeated, rather than zero padded for + * wide devices used in x8 mode. + */ + for (i =3D 1; i < pfl->max_device_width; i++) { + resp =3D deposit64(resp, 8 * i, 8, pfl->cfi_table[boff]); + } + } + /* Replicate responses for each device in bank. */ + if (pfl->device_width < pfl->bank_width) { + for (i =3D pfl->device_width; + i < pfl->bank_width; i +=3D pfl->device_width) { + resp =3D deposit64(resp, 8 * i, 8 * pfl->device_width, resp); + } + } + + return resp; +} + + + +static uint64_t _flash_read(pflash_t *pfl, hwaddr offset, + int width, int be) +{ + /* Flash area read */ + uint64_t ret =3D 0; + uint8_t *p =3D pfl->storage; + + switch (width) { + case 1: + ret =3D p[offset]; + /* DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); = */ + break; + case 2: + if (be) { + ret =3D p[offset] << 8; + ret |=3D p[offset + 1]; + } else { + ret =3D p[offset]; + ret |=3D p[offset + 1] << 8; + } + /* DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); = */ + break; + case 4: + if (be) { + ret =3D p[offset] << 24; + ret |=3D p[offset + 1] << 16; + ret |=3D p[offset + 2] << 8; + ret |=3D p[offset + 3]; + } else { + ret =3D p[offset]; + ret |=3D p[offset + 1] << 8; + ret |=3D p[offset + 2] << 16; + ret |=3D p[offset + 3] << 24; + } + /* DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); = */ + break; + case 8: + if (be) { + ret =3D (uint64_t)p[offset] << 56; + ret |=3D (uint64_t)p[offset + 1] << 48; + ret |=3D (uint64_t)p[offset + 2] << 40; + ret |=3D (uint64_t)p[offset + 3] << 32; + ret |=3D (uint64_t)p[offset + 4] << 24; + ret |=3D (uint64_t)p[offset + 5] << 16; + ret |=3D (uint64_t)p[offset + 6] << 8; + ret |=3D (uint64_t)p[offset + 7]; + } else { + ret =3D (uint64_t)p[offset]; + ret |=3D (uint64_t)p[offset + 1] << 8; + ret |=3D (uint64_t)p[offset + 2] << 16; + ret |=3D (uint64_t)p[offset + 3] << 24; + ret |=3D (uint64_t)p[offset + 4] << 32; + ret |=3D (uint64_t)p[offset + 5] << 40; + ret |=3D (uint64_t)p[offset + 6] << 48; + ret |=3D (uint64_t)p[offset + 7] << 56; + } + break; + } + + return ret; +} + +/* Perform a device id query based on the bank width of the flash. */ +static uint64_t pflash_devid_query(pflash_t *pfl, hwaddr offset, + int width, int be) +{ + int i; + uint64_t resp; + hwaddr boff; + + /* Adjust incoming offset to match expected device-width + * addressing. Device ID read addresses are always specified in + * terms of the maximum supported width of the device. This means + * that x8 devices and x8/x16 devices in x8 mode behave + * differently. For devices that are not used at their max width, + * we will be provided with addresses that use higher address bits + * than expected (based on the max width), so we will shift them + * lower so that they will match the addresses used when + * device_width=3D=3Dmax_device_width. + */ + boff =3D offset >> (ctz32(pfl->bank_width) + + ctz32(pfl->max_device_width) - ctz32(pfl->device_wid= th)); + + /* Mask off upper bits which may be used in to query block + * or sector lock status at other addresses. + */ + switch (boff & 0xFF) { + case 0: + resp =3D pfl->ident0; + DPRINTF("%s: Manufacturer Code %04x\n", __func__, resp); + break; + case 1: + resp =3D pfl->ident1; + DPRINTF("%s: Device ID Code %04x\n", __func__, resp); + break; + case 2: + resp =3D 0x00; /* Pretend all sectors are unprotected */ + break; + case 0xE: + case 0xF: + resp =3D boff & 0x01 ? pfl->ident3 : pfl->ident2; + if (resp !=3D (uint8_t)-1) { + break; + } + default: + return _flash_read(pfl, offset, width, be); + } + /* Replicate responses for each device in bank. */ + if (pfl->device_width < pfl->bank_width) { + for (i =3D pfl->device_width; + i < pfl->bank_width; i +=3D pfl->device_width) { + resp =3D deposit64(resp, 8 * i, 8 * pfl->device_width, resp); + } + } + + return resp; +} + + +static uint64_t pflash_read(pflash_t *pfl, hwaddr offset, + int width, int be) +{ + hwaddr boff; + uint64_t ret; + int i; =20 DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); ret =3D -1; @@ -154,10 +338,12 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr of= fset, } offset &=3D pfl->chip_len - 1; boff =3D offset & 0xFF; - if (pfl->width =3D=3D 2) + if (pfl->bank_width =3D=3D 2) boff =3D boff >> 1; - else if (pfl->width =3D=3D 4) + else if (pfl->bank_width =3D=3D 4) boff =3D boff >> 2; + else if (pfl->bank_width =3D=3D 8) + boff =3D boff >> 3; switch (pfl->cmd) { default: /* This should never happen : reset state & treat it as a read*/ @@ -168,77 +354,83 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr of= fset, case 0x80: /* We accept reads during second unlock sequence... */ case 0x00: - flash_read: - /* Flash area read */ - p =3D pfl->storage; - switch (width) { - case 1: - ret =3D p[offset]; -// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret= ); - break; - case 2: - if (be) { - ret =3D p[offset] << 8; - ret |=3D p[offset + 1]; - } else { - ret =3D p[offset]; - ret |=3D p[offset + 1] << 8; - } -// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret= ); - break; - case 4: - if (be) { - ret =3D p[offset] << 24; - ret |=3D p[offset + 1] << 16; - ret |=3D p[offset + 2] << 8; - ret |=3D p[offset + 3]; - } else { - ret =3D p[offset]; - ret |=3D p[offset + 1] << 8; - ret |=3D p[offset + 2] << 16; - ret |=3D p[offset + 3] << 24; - } -// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret= ); - break; - } + ret =3D _flash_read(pfl, offset, width, be); break; case 0x90: /* flash ID read */ - switch (boff) { - case 0x00: - case 0x01: - ret =3D boff & 0x01 ? pfl->ident1 : pfl->ident0; - break; - case 0x02: - ret =3D 0x00; /* Pretend all sectors are unprotected */ - break; - case 0x0E: - case 0x0F: - ret =3D boff & 0x01 ? pfl->ident3 : pfl->ident2; - if (ret =3D=3D (uint8_t)-1) { - goto flash_read; + if (!pfl->device_width) { + /* Preserve old behavior if device width not specified */ + switch (boff) { + case 0x00: + case 0x01: + ret =3D boff & 0x01 ? pfl->ident1 : pfl->ident0; + break; + case 0x02: + ret =3D 0x00; /* Pretend all sectors are unprotected */ + break; + case 0x0E: + case 0x0F: + ret =3D boff & 0x01 ? pfl->ident3 : pfl->ident2; + if (ret !=3D (uint8_t)-1) { + break; + } + default: + ret =3D _flash_read(pfl, offset, width, be); + } + } else { + /* If we have a read larger than the bank_width, combine multi= ple + * manufacturer/device ID queries into a single response. + */ + int i; + for (i =3D 0; i < width; i +=3D pfl->bank_width) { + ret =3D deposit64(ret, i * 8, pfl->bank_width * 8, + pflash_devid_query(pfl, + offset + i * pfl->bank_w= idth, + width, be)); } - break; - default: - goto flash_read; } - DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); break; case 0xA0: case 0x10: case 0x30: /* Status register read */ ret =3D pfl->status; - DPRINTF("%s: status %x\n", __func__, ret); + for (i =3D pfl->device_width; + i < pfl->bank_width; i +=3D pfl->device_width) { + ret =3D deposit64(ret, 8 * i, 8 * pfl->device_width, ret); + } + DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); /* Toggle bit 6 */ pfl->status ^=3D 0x40; break; case 0x98: /* CFI query mode */ - if (boff > pfl->cfi_len) - ret =3D 0; - else - ret =3D pfl->cfi_table[boff]; + if (!pfl->device_width) { + /* Preserve old behavior if device width not specified */ + boff =3D offset & 0xFF; + if (pfl->bank_width =3D=3D 2) { + boff =3D boff >> 1; + } else if (pfl->bank_width =3D=3D 4) { + boff =3D boff >> 2; + } + + if (boff > pfl->cfi_len) { + ret =3D 0; + } else { + ret =3D pfl->cfi_table[boff]; + } + } else { + /* If we have a read larger than the bank_width, combine multi= ple + * CFI queries into a single response. + */ + int i; + for (i =3D 0; i < width; i +=3D pfl->bank_width) { + ret =3D deposit64(ret, i * 8, pfl->bank_width * 8, + pflash_cfi_query(pfl, + offset + i * pfl->bank_wi= dth)); + } + } + break; } =20 @@ -246,8 +438,7 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offs= et, } =20 /* update flash content on disk */ -static void pflash_update(pflash_t *pfl, int offset, - int size) +static void pflash_update(pflash_t *pfl, int offset, int size) { int offset_end; if (pfl->blk) { @@ -260,8 +451,8 @@ static void pflash_update(pflash_t *pfl, int offset, } } =20 -static void pflash_write (pflash_t *pfl, hwaddr offset, - uint32_t value, int width, int be) +static void pflash_write(pflash_t *pfl, hwaddr offset, + uint64_t value, int width, int be) { hwaddr boff; uint8_t *p; @@ -275,17 +466,19 @@ static void pflash_write (pflash_t *pfl, hwaddr offse= t, #endif goto reset_flash; } - DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, - offset, value, width, pfl->wcycle); + DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d %d\n", + __func__, offset, value, width, pfl->wcycle); offset &=3D pfl->chip_len - 1; =20 - DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, - offset, value, width); + DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d\n", + __func__, offset, value, width); boff =3D offset & (pfl->sector_len - 1); - if (pfl->width =3D=3D 2) + if (pfl->bank_width =3D=3D 2) boff =3D boff >> 1; - else if (pfl->width =3D=3D 4) + else if (pfl->bank_width =3D=3D 4) boff =3D boff >> 2; + else if (pfl->bank_width =3D=3D 8) + boff =3D boff >> 3; switch (pfl->wcycle) { case 0: /* Set the device in I/O access mode if required */ @@ -346,8 +539,8 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, /* We need another unlock sequence */ goto check_unlock0; case 0xA0: - DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", - __func__, offset, value, width); + DPRINTF("%s: write data offset " TARGET_FMT_plx + " %08" PRIx64 " %d\n", __func__, offset, value, width); p =3D pfl->storage; if (!pfl->ro) { switch (width) { @@ -379,6 +572,28 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, } pflash_update(pfl, offset, 4); break; + case 8: + if (be) { + p[offset] &=3D value >> 56; + p[offset + 1] &=3D value >> 48; + p[offset + 2] &=3D value >> 40; + p[offset + 3] &=3D value >> 32; + p[offset + 4] &=3D value >> 24; + p[offset + 5] &=3D value >> 16; + p[offset + 6] &=3D value >> 8; + p[offset + 7] &=3D value; + } else { + p[offset] &=3D value; + p[offset + 1] &=3D value >> 8; + p[offset + 2] &=3D value >> 16; + p[offset + 3] &=3D value >> 24; + p[offset + 4] &=3D value >> 32; + p[offset + 5] &=3D value >> 40; + p[offset + 6] &=3D value >> 48; + p[offset + 7] &=3D value >> 56; + } + pflash_update(pfl, offset, 8); + break; } } pfl->status =3D 0x00 | ~(value & 0x80); @@ -494,103 +709,46 @@ static void pflash_write (pflash_t *pfl, hwaddr offs= et, pfl->cmd =3D 0; } =20 - -static uint32_t pflash_readb_be(void *opaque, hwaddr addr) -{ - return pflash_read(opaque, addr, 1, 1); -} - -static uint32_t pflash_readb_le(void *opaque, hwaddr addr) -{ - return pflash_read(opaque, addr, 1, 0); -} - -static uint32_t pflash_readw_be(void *opaque, hwaddr addr) -{ - pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 2, 1); -} - -static uint32_t pflash_readw_le(void *opaque, hwaddr addr) +static uint64_t pflash_read_le(void *opaque, hwaddr addr, unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 2, 0); + return pflash_read(pfl, addr, size, 0); } =20 -static uint32_t pflash_readl_be(void *opaque, hwaddr addr) +static uint64_t pflash_read_be(void *opaque, hwaddr addr, unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 4, 1); + return pflash_read(pfl, addr, size, 1); } =20 -static uint32_t pflash_readl_le(void *opaque, hwaddr addr) +static void pflash_write_le(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { pflash_t *pfl =3D opaque; - - return pflash_read(pfl, addr, 4, 0); + pflash_write(pfl, addr, data, size, 0); } =20 -static void pflash_writeb_be(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_write(opaque, addr, value, 1, 1); -} - -static void pflash_writeb_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_write(opaque, addr, value, 1, 0); -} - -static void pflash_writew_be(void *opaque, hwaddr addr, - uint32_t value) +static void pflash_write_be(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 2, 1); -} - -static void pflash_writew_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 2, 0); -} - -static void pflash_writel_be(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 4, 1); -} - -static void pflash_writel_le(void *opaque, hwaddr addr, - uint32_t value) -{ - pflash_t *pfl =3D opaque; - - pflash_write(pfl, addr, value, 4, 0); + pflash_write(pfl, addr, data, size, 1); } =20 static const MemoryRegionOps pflash_cfi02_ops_be =3D { - .old_mmio =3D { - .read =3D { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, - .write =3D { pflash_writeb_be, pflash_writew_be, pflash_writel_be,= }, - }, + .read =3D pflash_read_be, + .write =3D pflash_write_be, .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.max_access_size =3D 8, + .impl.max_access_size =3D 8, }; =20 static const MemoryRegionOps pflash_cfi02_ops_le =3D { - .old_mmio =3D { - .read =3D { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, - .write =3D { pflash_writeb_le, pflash_writew_le, pflash_writel_le,= }, - }, + .read =3D pflash_read_le, + .write =3D pflash_write_le, .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.max_access_size =3D 8, + .impl.max_access_size =3D 8, }; =20 static void pflash_cfi02_realize(DeviceState *dev, Error **errp) @@ -654,6 +812,13 @@ static void pflash_cfi02_realize(DeviceState *dev, Err= or **errp) } } =20 + /* Default to devices being used at their maximum device width. This w= as + * assumed before the device_width support was added. + */ + if (!pfl->max_device_width) { + pfl->max_device_width =3D pfl->device_width; + } + pflash_setup_mappings(pfl); pfl->rom_mode =3D 1; sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); @@ -745,7 +910,25 @@ static Property pflash_cfi02_properties[] =3D { DEFINE_PROP_DRIVE("drive", struct pflash_t, blk), DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0), - DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), + /* width here is the overall width of this QEMU device in bytes. + * The QEMU device may be emulating a number of flash devices + * wired up in parallel; the width of each individual flash + * device should be specified via device-width. If the individual + * devices have a maximum width which is greater than the width + * they are being used for, this maximum width should be set via + * max-device-width (which otherwise defaults to device-width). + * So for instance a 32-bit wide QEMU flash device made from four + * 16-bit flash devices used in 8-bit wide mode would be configured + * with width =3D 4, device-width =3D 1, max-device-width =3D 2. + * + * If device-width is not specified we default to backwards + * compatible behaviour which is a bad emulation of two + * 16 bit devices making up a 32 bit wide QEMU device. This + * is deprecated for new uses of this device. + */ + DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), + DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0), + DEFINE_PROP_UINT8("max-device-width", struct pflash_t, max_device_widt= h, 0), DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0), DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), @@ -785,7 +968,7 @@ pflash_t *pflash_cfi02_register(hwaddr base, DeviceState *qdev, const char *name, hwaddr size, BlockBackend *blk, uint32_t sector_len, - int nb_blocs, int nb_mappings, int width, + int nb_blocs, int nb_mappings, int bank_wi= dth, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t unlock_addr0, uint16_t unlock_add= r1, @@ -798,7 +981,7 @@ pflash_t *pflash_cfi02_register(hwaddr base, } qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); qdev_prop_set_uint32(dev, "sector-length", sector_len); - qdev_prop_set_uint8(dev, "width", width); + qdev_prop_set_uint8(dev, "width", bank_width); qdev_prop_set_uint8(dev, "mappings", nb_mappings); qdev_prop_set_uint8(dev, "big-endian", !!be); qdev_prop_set_uint16(dev, "id0", id0); --=20 2.14.2