From nobody Mon May 6 11:23:25 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510155314164148.4744657473002; Wed, 8 Nov 2017 07:35:14 -0800 (PST) Received: from localhost ([::1]:60468 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSNU-0001WY-SB for importer@patchew.org; Wed, 08 Nov 2017 10:34:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34279) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSLX-0000PI-Ku for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCSLR-00026U-F4 for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:55 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:54596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eCSLR-00025i-70 for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:49 -0500 Received: by mail-wm0-x244.google.com with SMTP id r68so11663995wmr.3 for ; Wed, 08 Nov 2017 07:32:49 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 89sm1383472wri.79.2017.11.08.07.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 07:32:46 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B5F8F3E03B5; Wed, 8 Nov 2017 15:32:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RdjZVKDXF1lYZFRSoSg7iXRmw6zd1GpA/QRInYksgwQ=; b=cqhKza+XajA6MQu/EHGcDb6OkLDkFo3U/kL/BFyABy020R0YlDKbzMj2f9VwfDvnvg DdTzzfzzbIuVpi5fGAnUeYejLr+Q6IbSu3dtoGJQxM5tCosNNM1/HA4FdPYc/JRT4qYF Z8lT9OVJrbyonmbTYv5Sn1wZ+fgnyhOtUx++c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RdjZVKDXF1lYZFRSoSg7iXRmw6zd1GpA/QRInYksgwQ=; b=XJu1bR9PYuD/44MtI7ch2Pc2159ph2ylLxqDJmKeybcmFtAc2IjCrUefSI1vwSdDnu wWknV0C4MO1dZtRJyFDKDUsN44mePNjz5e/gax+jWQESdz6zJBaFwitSHI4cJ9zHDtWq rkw2zlMKbtPVtCtbB6f2cz7te6ODRMDVbpeiyF9FtF4gTrLTfs30Qpmxd4J954f0NJbD 6daRNSSH+k2hd/oOJlXp3FX4w+HUolIHAbYGTo0tGb7kcuVigd5NvOl6EVylPnDj+LzW kVULM7huQnlp4fd4Y+1xpxFtRYzNDONVoMveZt2/Rd3szIsuUuIwyq0SPy3dFrq/cbV6 nMww== X-Gm-Message-State: AJaThX7hJC1G0xIokjWXhkttlcrr7jjFHyZsEyCfXCgIWdp6T2g8+qaE MD9RGUdGN/akx0RxELXT/rczMA== X-Google-Smtp-Source: ABhQp+TnVHBglIzw2y527FYvzKqKw661d5LlVjFlyA3Jclk2PVfSKMgWBPxTrLb8tnEcv7IUjQRufg== X-Received: by 10.28.131.200 with SMTP id f191mr775322wmd.39.1510155167897; Wed, 08 Nov 2017 07:32:47 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 8 Nov 2017 15:32:44 +0000 Message-Id: <20171108153245.20740-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171108153245.20740-1-alex.bennee@linaro.org> References: <20171108153245.20740-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v2 1/2] accel/tcg/translate-all: expand cpu_restore_state addr check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 We are still seeing signals during translation time when we walk over a page protection boundary. This expands the check to ensure the host PC is inside the code generation buffer. The original suggestion was to check versus tcg_ctx.code_gen_ptr but as we now segment the translation buffer we have to settle for just a general check for being inside. I've also fixed up the declaration to make it clear it can deal with invalid addresses. A later patch will fix up the call sites. Signed-off-by: Alex Benn=C3=A9e Reported-by: Peter Maydell Suggested-by: Paolo Bonzini Cc: Richard Henderson Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson --- v2: - add doc comment to exec-all.h - retaddr->host_pc - re-word comments on host_pc - simplify logic as per rth suggestion --- accel/tcg/translate-all.c | 52 ++++++++++++++++++++++++++-----------------= ---- include/exec/exec-all.h | 11 ++++++++++ 2 files changed, 40 insertions(+), 23 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 34c5e28d07..e7f0329a52 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -352,36 +352,42 @@ static int cpu_restore_state_from_tb(CPUState *cpu, T= ranslationBlock *tb, return 0; } =20 -bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) { TranslationBlock *tb; bool r =3D false; + uintptr_t check_offset; =20 - /* A retaddr of zero is invalid so we really shouldn't have ended - * up here. The target code has likely forgotten to check retaddr - * !=3D 0 before attempting to restore state. We return early to - * avoid blowing up on a recursive tb_lock(). The target must have - * previously survived a failed cpu_restore_state because - * tb_find_pc(0) would have failed anyway. It still should be - * fixed though. + /* The host_pc has to be in the region of current code buffer. If + * it is not we will not be able to resolve it here. The two cases + * where host_pc will not be correct are: + * + * - fault during translation (instruction fetch) + * - fault from helper (not using GETPC() macro) + * + * Either way we need return early to avoid blowing up on a + * recursive tb_lock() as we can't resolve it here. + * + * We are using unsigned arithmetic so if host_pc < + * tcg_init_ctx.code_gen_buffer check_offset will wrap to way + * above the code_gen_buffer_size */ - - if (!retaddr) { - return r; - } - - tb_lock(); - tb =3D tb_find_pc(retaddr); - if (tb) { - cpu_restore_state_from_tb(cpu, tb, retaddr); - if (tb->cflags & CF_NOCACHE) { - /* one-shot translation, invalidate it immediately */ - tb_phys_invalidate(tb, -1); - tb_remove(tb); + check_offset =3D host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; + + if (check_offset < tcg_init_ctx.code_gen_buffer_size) { + tb_lock(); + tb =3D tb_find_pc(host_pc); + if (tb) { + cpu_restore_state_from_tb(cpu, tb, host_pc); + if (tb->cflags & CF_NOCACHE) { + /* one-shot translation, invalidate it immediately */ + tb_phys_invalidate(tb, -1); + tb_remove(tb); + } + r =3D true; } - r =3D true; + tb_unlock(); } - tb_unlock(); =20 return r; } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 923ece3e9b..0f51c92adb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -45,6 +45,17 @@ void restore_state_to_opc(CPUArchState *env, struct Tran= slationBlock *tb, target_ulong *data); =20 void cpu_gen_init(void); + +/** + * cpu_restore_state: + * @cpu: the vCPU state is to be restore to + * @searched_pc: the host PC the fault occurred at + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If the searched_pc is not in translated code no state is + * restored and the function returns false. + */ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); =20 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); --=20 2.14.2 From nobody Mon May 6 11:23:25 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510155326510419.3011142775795; Wed, 8 Nov 2017 07:35:26 -0800 (PST) Received: from localhost ([::1]:60470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSNl-0001gO-Iq for importer@patchew.org; Wed, 08 Nov 2017 10:35:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eCSLU-0000Oc-CQ for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eCSLS-00027L-JF for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:52 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:48682) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eCSLS-00026i-9P for qemu-devel@nongnu.org; Wed, 08 Nov 2017 10:32:50 -0500 Received: by mail-wr0-x243.google.com with SMTP id 15so2787139wrb.5 for ; Wed, 08 Nov 2017 07:32:50 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c67sm3092003wmd.25.2017.11.08.07.32.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 07:32:48 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id D58F43E0410; Wed, 8 Nov 2017 15:32:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7aFad4r50/2gvUyQSqJuUtcxZtJrnOrFdDD3nkmtwFM=; b=QJfwbiD6WVgmPoLLX1eoMZVe6AFhhiiJIFXdeMywY1D3rMPcZIQRbUH4LuClvSXXoo 2j2fAI1gZ+zjPpB3d1mDbmx9LgTFX2+N54TNN+KOpJe4ERPi7ee9+oCbs9x6PVGp/8sf hh4HsfAagWAwCjVoRIBtMkRqSCaS+XUhV6L18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7aFad4r50/2gvUyQSqJuUtcxZtJrnOrFdDD3nkmtwFM=; b=WhLDkZyN/RVLbicwjLDOT3XxHZQvjk6IoIXH+iWXdkcwfFkpzAXl/bmR899XRJnHzX MNmcaPolj2ux1EiSixF7ZKeP4t66yczmtlpl4vHIjnSYJLFKhcXp7TuR0hvgyXPtjVjZ +AkWCpx6T6fZOu70yFuP6JKW6t3UOI8kjb5v2bnAbsSpaDsd+9ZbRYbMOfhLxFywL2pa qc0R/7cKimTdCQ/CEvANiTGiqBF0Ziwg62/+AkuCB/d8mne/YrVBDZb80EH0UO8NrwrE vycevEObWkakx+8EN8QU0P0xT4Uh0jgP5Cf48q1+zYRzvffkyVvrYAwoTscOFl2Y3KvH 4wvw== X-Gm-Message-State: AJaThX6c74wkV23NGFCe0qvn43IhgKEc1y2inUyQ3P/VC37jmI2LU7uf 22iNdz9Tjaub7gK6r+V5AyJOZg== X-Google-Smtp-Source: ABhQp+S1tAzxrbGw8F58hkJmvvZwbxsU0PgOokJTaVJAvroIMEaWjlIR7f1XpcePEkeBtZa54w9Y/Q== X-Received: by 10.223.186.202 with SMTP id w10mr884505wrg.132.1510155169080; Wed, 08 Nov 2017 07:32:49 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 8 Nov 2017 15:32:45 +0000 Message-Id: <20171108153245.20740-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171108153245.20740-1-alex.bennee@linaro.org> References: <20171108153245.20740-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 2/2] target/*helper: don't check retaddr before calling cpu_restore_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Alexander Graf , Eduardo Habkost , "open list:S390" , Bastian Koppelmann , Anthony Green , Chris Wulff , qemu-devel@nongnu.org, Laurent Vivier , Michael Walle , qemu-arm@nongnu.org, "Edgar E. Iglesias" , Paolo Bonzini , Stafford Horne , Guan Xuetao , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson --- scripts/coccinelle/cpu_restore_state.cocci | 12 ++++++++++++ target/alpha/mem_helper.c | 12 +++--------- target/arm/op_helper.c | 17 ++++------------- target/i386/svm_helper.c | 4 +--- target/lm32/op_helper.c | 7 ++----- target/m68k/op_helper.c | 7 ++----- target/microblaze/op_helper.c | 7 ++----- target/moxie/helper.c | 4 +--- target/nios2/mmu.c | 7 ++----- target/openrisc/mmu_helper.c | 7 ++----- target/s390x/excp_helper.c | 4 +--- target/tricore/op_helper.c | 11 +++-------- target/unicore32/op_helper.c | 7 ++----- 13 files changed, 37 insertions(+), 69 deletions(-) create mode 100644 scripts/coccinelle/cpu_restore_state.cocci diff --git a/scripts/coccinelle/cpu_restore_state.cocci b/scripts/coccinell= e/cpu_restore_state.cocci new file mode 100644 index 0000000000..934a042382 --- /dev/null +++ b/scripts/coccinelle/cpu_restore_state.cocci @@ -0,0 +1,12 @@ +// Remove unneeded tests before calling cpu_restore_state +// +// spatch --macro-file scripts/cocci-macro-file.h \ +// --sp-file ./scripts/coccinelle/cpu_restore_state.cocci \ +// --keep-comments --in-place --use-gitgrep --dir target +@@ +identifier A; +expression C; +@@ +-if (A) { + cpu_restore_state(C, A); +-} diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 3c06baa93a..6cf9bba17e 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -34,9 +34,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr ad= dr, uint64_t pc; uint32_t insn; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 pc =3D env->pc; insn =3D cpu_ldl_code(env, pc); @@ -58,9 +56,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 env->trap_arg0 =3D addr; env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; @@ -80,9 +76,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 ret =3D alpha_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret !=3D 0)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); /* Exception index and error code are already set */ cpu_loop_exit(cs); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index a40a84ac24..504556a697 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -175,11 +175,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, if (unlikely(ret)) { ARMCPU *cpu =3D ARM_CPU(cs); uint32_t fsc; - - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); =20 if (fsr & (1 << 9)) { /* LPAE format fault status register : bottom 6 bits are @@ -210,11 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, uint32_t fsr, fsc; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); - - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format @@ -244,11 +238,8 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, uint32_t fsr, fsc; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); - - if (retaddr) { /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 /* The EA bit in syndromes and fault status registers is an * IMPDEF classification of external aborts. ARM implementations diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index f479239875..303106981c 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -584,9 +584,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, u= int64_t exit_info_1, { CPUState *cs =3D CPU(x86_env_get_cpu(env)); =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); =20 qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" PRIx64 ", " TARGET_FMT_lx ")!\n", diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 2177c8ad12..7b800bbeab 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -150,11 +150,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, int ret; =20 ret =3D lm32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 63089511cb..3079e04c7d 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -45,11 +45,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, int ret; =20 ret =3D m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1e07e21c1c..3b862faaa1 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -39,11 +39,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, int ret; =20 ret =3D mb_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 330299f5a7..2ecee89f11 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -36,9 +36,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessT= ype access_type, =20 ret =3D moxie_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); } cpu_loop_exit(cs); } diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index fe9298af50..6d66a5702d 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -41,11 +41,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, int ret; =20 ret =3D nios2_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a44d0aa51a..47cd7775b6 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -32,11 +32,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccess= Type access_type, =20 ret =3D openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); =20 - if (ret) { - if (retaddr) { - /* now we have a real cpu fault. */ - cpu_restore_state(cs, retaddr); - } + if (ret) {/* now we have a real cpu fault. */ + cpu_restore_state(cs, retaddr); /* Raise Exception. */ cpu_loop_exit(cs); } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index e04b670663..8584ec43c1 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -554,9 +554,7 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; =20 - if (retaddr) { - cpu_restore_state(cs, retaddr); - } + cpu_restore_state(cs, retaddr); program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); } =20 diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 7af202c8c0..b0307de1ea 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -31,9 +31,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint3= 2_t class, int tin, { CPUState *cs =3D CPU(tricore_env_get_cpu(env)); /* in case we come from a helper-call we need to restore the PC */ - if (pc) { - cpu_restore_state(cs, pc); - } + cpu_restore_state(cs, pc); =20 /* Tin is loaded into d[15] */ env->gpr_d[15] =3D tin; @@ -2804,11 +2802,8 @@ static inline void QEMU_NORETURN do_raise_exception_= err(CPUTriCoreState *env, CPUState *cs =3D CPU(tricore_env_get_cpu(env)); cs->exception_index =3D exception; env->error_code =3D error_code; - - if (pc) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, pc); - } + /* now we have a real cpu fault */ + cpu_restore_state(cs, pc); =20 cpu_loop_exit(cs); } diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index 0872c29faa..5a826b0e31 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -250,11 +250,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcce= ssType access_type, int ret; =20 ret =3D uc32_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr); - } + if (unlikely(ret)) {/* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); cpu_loop_exit(cs); } } --=20 2.14.2