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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.16.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I8knqKtDtrPPdB7wZkda44RkOSyjS1Nf4JPvku5r/yQ=; b=DcCGXBS6r1/klYaz0a5mH3Y+1bVvYJ1rWSOIhyuUBIVwj3a3x+pNqWzqkwdEg997II EKYRLaX8enP/QG0iMm12mrvSAxUwKsGKo7Syk06POavNU/O6M+J+ey3S+IYtAAvSDkk4 rocATbcVFJmj7NiK3ptr18IY7u/g7aevfL/FM5GADzA7DJQMSWmI6+rbk2m7aphg+xl6 mw/3l+Tgia8Ukh26M29x2DSWJqBfZg7P0t+9jaYYMioBqUHG3KKafNUDgKANWkBnSxRz cOY2U+1aoPfep68BE1WKJjgQ/RHgEkvtLBONPHv9v9uGgMcXoveuddGSrG3tfIDYYjwh l2Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I8knqKtDtrPPdB7wZkda44RkOSyjS1Nf4JPvku5r/yQ=; b=jeC4NeCWga0bGWtZHOENihso9y2MqXkO0+pFmVoE9b6b74Vun29ClrJodUnY1kLqUs dBEoXJ9tr+njeGMyShqg7B9W9qOs8waBN79OiIO2pgi11OyNc40EdkzNfvvC+NAH6PSA PW6lRd4/TGPjsUz2D3PiITWxegj4PdDUoC8xCxNFqvn2JRs9nAqne9KWc4BWe/3D4jlk BHDwg4tqjxsNtAHZKD9XZpWysf8RXpbxSXxpR59qut5WZd+TkDORMZStHKc2c0Rgx50U 8k3tzzkavmQGXWNstkZMw5tmvMjqFLfrtzX5sfv26AosO1S4J/kwqq2GKQ4prxBgdEQO RUGw== X-Gm-Message-State: AMCzsaUoQqYrsR7bluqMD6YqK9VE5DR5uMzUySixfNxaCseC5p7zX7id 32872gCgWZwwf8zM9sCr6HrsaA== X-Google-Smtp-Source: ABhQp+SfOth9PhEP0lUAdXmQ3VXWDi1I+Sko5bn9X7PEEegGEKJLaoStoh2nOJqu6i0IHRic/GG1FQ== X-Received: by 10.25.22.78 with SMTP id m75mr1826803lfi.20.1509520617526; Wed, 01 Nov 2017 00:16:57 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:40 +0100 Message-Id: <20171101071652.19375-2-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v6 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice, Eon and Macronix. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a2438b9..721ae1a 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -423,6 +423,7 @@ typedef struct Flash { uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; uint32_t len; uint32_t pos; + bool data_read_loop; uint8_t needed_bytes; uint8_t cmd_in_progress; uint32_t cur_addr; @@ -983,6 +984,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -993,6 +995,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -1133,6 +1136,7 @@ static int m25p80_cs(SSISlave *ss, bool select) s->pos =3D 0; s->state =3D STATE_IDLE; flash_sync_dirty(s, -1); + s->data_read_loop =3D false; } =20 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); @@ -1198,7 +1202,9 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32= _t tx) s->pos++; if (s->pos =3D=3D s->len) { s->pos =3D 0; - s->state =3D STATE_IDLE; + if (!s->data_read_loop) { + s->state =3D STATE_IDLE; + } } break; =20 @@ -1279,6 +1285,7 @@ static const VMStateDescription vmstate_m25p80 =3D { VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), VMSTATE_UINT32(len, Flash), VMSTATE_UINT32(pos, Flash), + VMSTATE_BOOL(data_read_loop, Flash), VMSTATE_UINT8(needed_bytes, Flash), VMSTATE_UINT8(cmd_in_progress, Flash), VMSTATE_UINT32(cur_addr, Flash), --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509520919932147.38983140021514; Wed, 1 Nov 2017 00:21:59 -0700 (PDT) Received: from localhost ([::1]:48715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nLZ-0001AX-42 for importer@patchew.org; Wed, 01 Nov 2017 03:21:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGn-00065m-Fi for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGm-0001Nx-HD for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:01 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:54695) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGm-0001Ma-9B for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:00 -0400 Received: by mail-lf0-x243.google.com with SMTP id a2so1459514lfh.11 for ; Wed, 01 Nov 2017 00:17:00 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.16.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xp+/WDqEVLZMACbxE1YLTKO+/ozRbfDBnug4bO87NoY=; b=I5UgSzMowYY1Y0mReVxqz/yRaBmTnz/FOw66kA3ZkoUoOXx9zSMjOWq+4Q3PRxOAhh s2svBGgpzTVTgWG25MmKTU22uV/CWRxiJI2NmDuiXZS+8uCjttY4OaffWUtIMaEMY1KE L/PG1p5g7dAjh5AukovjUDnMI1nXHAp8CIGbw77avAGrE2YqL813pBMEkj8LcJ8e05+b UlzdgxLtc+VzyH06/opS0dlRjofPFzJ0uFoUjFKhxSwf9ePnBp/thb9z5dPPou2vNTjB MiNQfIvlkOJ3U9A0ov93UcvwiIaXoCbromPG36uI9IZ4aC8PEu+zkVIkS8YuFPJNQh55 8PBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xp+/WDqEVLZMACbxE1YLTKO+/ozRbfDBnug4bO87NoY=; b=K/SHKkqIGJuURDdhGWWXqRn7aQ5fJ1OqS+NNig/dr54i3DR3znDtCErTvR1bgw36ju HBCVfffCV9LTu2qd3vEuy0/LkGUct212hKa124Ef3MFO7hIP36f0XYnnhvYSPBqjUyFe Hxe2Cht9HZ7OEt3qxtUfqiSfyuhXIBxsrKBzYePs1Tn4/ycY2TEq1MOL1NZQSwN64+Qn uWJNE7fW2sYLNCiV82W2pXtYuTqJqbAbV84zUDF0qK0NfXMKAwG5fF/l1KKeXAT12zWE vC8ot9ynQ8ERaPYvSkGVV2AQswTOZ1Smcz8eUxq3eqLY/tr45X+ye+p006Nmo94hmAwc pnVA== X-Gm-Message-State: AMCzsaWOXTWjnh7j+9mLylVm6E2uBpzOpIlQqhgpuD84S7sUrgUKQtmW gtJ+hpronaly8XA+q9v0P42gnw== X-Google-Smtp-Source: ABhQp+S/QU46FR260O9pRS+2vkTuzORAEzkNBQ7a2alm+E/Tgej0LDxo2d9ca3NMW/K3n7J2ui/eSg== X-Received: by 10.25.217.26 with SMTP id q26mr1732200lfg.52.1509520618773; Wed, 01 Nov 2017 00:16:58 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:41 +0100 Message-Id: <20171101071652.19375-3-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Acked-by: Marcin Krzemi=C5=84ski --- hw/block/m25p80.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 721ae1a..12ff656 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -355,6 +355,8 @@ typedef enum { DPP =3D 0xa2, QPP =3D 0x32, QPP_4 =3D 0x34, + RDID_90 =3D 0x90, + RDID_AB =3D 0xab, =20 ERASE_4K =3D 0x20, ERASE4_4K =3D 0x21, @@ -405,6 +407,7 @@ typedef enum { MAN_MACRONIX, MAN_NUMONYX, MAN_WINBOND, + MAN_SST, MAN_GENERIC, } Manufacturer; =20 @@ -476,6 +479,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_SPANSION; case 0xC2: return MAN_MACRONIX; + case 0xBF: + return MAN_SST; default: return MAN_GENERIC; } @@ -711,6 +716,22 @@ static void complete_collecting_data(Flash *s) case WEVCR: s->enh_volatile_cfg =3D s->data[0]; break; + case RDID_90: + case RDID_AB: + if (get_man(s) =3D=3D MAN_SST && s->cur_addr <=3D 1) { + if (s->cur_addr) { + s->data[0] =3D s->pi->id[2]; + s->data[1] =3D s->pi->id[0]; + } else { + s->data[0] =3D s->pi->id[0]; + s->data[1] =3D s->pi->id[2]; + } + s->pos =3D 0; + s->len =3D 2; + s->data_read_loop =3D true; + s->state =3D STATE_READING_DATA; + } + break; default: break; } @@ -926,6 +947,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) case PP4: case PP4_4: case DIE_ERASE: + case RDID_90: + case RDID_AB: s->needed_bytes =3D get_addr_length(s); s->pos =3D 0; s->len =3D 0; --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509521289342527.6123205965647; Wed, 1 Nov 2017 00:28:09 -0700 (PDT) Received: from localhost ([::1]:48742 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nRW-00061H-JG for importer@patchew.org; Wed, 01 Nov 2017 03:28:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGu-0006BG-9l for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGn-0001Pr-Qy for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:08 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:55908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGn-0001OS-JX for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:01 -0400 Received: by mail-lf0-x243.google.com with SMTP id e143so1459096lfg.12 for ; Wed, 01 Nov 2017 00:17:01 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski --- hw/block/m25p80.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 12ff656..3f8154b 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -331,7 +331,10 @@ typedef enum { WRDI =3D 0x4, RDSR =3D 0x5, WREN =3D 0x6, + BRRD =3D 0x16, + BRWR =3D 0x17, JEDEC_READ =3D 0x9f, + BULK_ERASE_60 =3D 0x60, BULK_ERASE =3D 0xc7, READ_FSR =3D 0x70, RDCR =3D 0x15, @@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s) s->write_enable =3D false; } break; + case BRWR: case EXTEND_ADDR_WRITE: s->ear =3D s->data[0]; break; @@ -1041,6 +1045,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state =3D STATE_READING_DATA; break; =20 + case BULK_ERASE_60: case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); @@ -1058,12 +1063,14 @@ static void decode_new_cmd(Flash *s, uint32_t value) case EX_4BYTE_ADDR: s->four_bytes_address_mode =3D false; break; + case BRRD: case EXTEND_ADDR_READ: s->data[0] =3D s->ear; s->pos =3D 0; s->len =3D 1; s->state =3D STATE_READING_DATA; break; + case BRWR: case EXTEND_ADDR_WRITE: if (s->write_enable) { s->needed_bytes =3D 1; --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509520814989549.8567458222825; Wed, 1 Nov 2017 00:20:14 -0700 (PDT) Received: from localhost ([::1]:48702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nJs-0008DO-56 for importer@patchew.org; Wed, 01 Nov 2017 03:20:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGq-00066Y-7S for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGp-0001R2-1y for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:04 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:49942) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGo-0001Q4-RM for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:02 -0400 Received: by mail-lf0-x243.google.com with SMTP id w21so1480355lfc.6 for ; Wed, 01 Nov 2017 00:17:02 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 04/13] m25p80: Add support for n25q512a11 and n25q512a13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Reviewed-by: Alistair Francis --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 3f8154b..2f66537 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -240,6 +240,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, + { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509521081124586.0546638329166; Wed, 1 Nov 2017 00:24:41 -0700 (PDT) Received: from localhost ([::1]:48726 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nNz-0003JT-DM for importer@patchew.org; Wed, 01 Nov 2017 03:24:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGr-000683-Jm for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGq-0001Rr-Ck for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:05 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:44605) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGq-0001RR-59 for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:04 -0400 Received: by mail-lf0-x243.google.com with SMTP id 75so1491401lfx.1 for ; Wed, 01 Nov 2017 00:17:04 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency (struct XilinxSPIPS is found there). Also move out a define and remove two dubbel included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 35 ----------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..559fa79 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,44 +114,11 @@ =20 /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 =20 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 =20 -typedef enum { - READ =3D 0x3, - FAST_READ =3D 0xb, - DOR =3D 0x3b, - QOR =3D 0x6b, - DIOR =3D 0xbb, - QIOR =3D 0xeb, - - PP =3D 0x2, - DPP =3D 0xa2, - QPP =3D 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; - static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) =20 +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ =3D 0x3, READ_4 =3D 0x13, + FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, + DOR =3D 0x3b, DOR_4 =3D 0x3c, + QOR =3D 0x6b, QOR_4 =3D 0x6c, + DIOR =3D 0xbb, DIOR_4 =3D 0xbc, + QIOR =3D 0xeb, QIOR_4 =3D 0xec, + + PP =3D 0x2, PP_4 =3D 0x12, + DPP =3D 0xa2, + QPP =3D 0x32, QPP_4 =3D 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; =20 @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; =20 +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" =20 --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 150952119575478.82077969801776; Wed, 1 Nov 2017 00:26:35 -0700 (PDT) Received: from localhost ([::1]:48735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nPx-0004x8-UZ for importer@patchew.org; Wed, 01 Nov 2017 03:26:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54437) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGt-00069U-2n for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGs-0001TR-2W for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:07 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:53031) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGr-0001S0-Qr for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:05 -0400 Received: by mail-lf0-x244.google.com with SMTP id b190so1468633lfg.9 for ; Wed, 01 Nov 2017 00:17:05 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g28/VxI+Kg3Svfb39x2djiyH/8fi6IifKHaPcH4wdiU=; b=UYz8rAlxP+Y8HurRAHtQbSlEX+TI8HBMPu+OvNRc8EjS2ci8/JqXtdu3z3PloIMSmC 5to0BvdJ3dHat9XqdkjRV+sM6UyXd5FKziSUdxkGrL6JpqyAwXLeU48LZ0x8xK78yHtZ ZT39GUej3Ar/KHTsKqR4yQE+kllRDTic1uU9+ZfNBEUEoi6g6CB5G4ltHZgBENd1IG7f 8vAj12CgF+3x/EvWnXM7LBpmOzj5KePWv/1MHOVbufo7x+KQu9LlVIeqYgltjBWVwYMe rbEmHY98SVIK8CprKEFsydvPX7QeQ658C3T2+YX4Eq3c0/hYeobNUk81Veh8LdWGVvIb qZFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g28/VxI+Kg3Svfb39x2djiyH/8fi6IifKHaPcH4wdiU=; b=lGiUFsLlVmzkMjDY9gs1sqHpRfwOW+9JJ8K5/MDfHKDADyUFSXLgsxpBPOvbbXqruW NKm/TYqV0wZwGgfrmJ2bVb3wsK/ZaTf9MpSyPjzOOqsFOTFrjApUuaptftqNcDC7R5Tq 5Au2q13oU69GDuqhUvipUcKGvcdyJ4lvuW4veRavenUH1ONRFOq1s1WJenkmUiaZetYy hY36YeE+jIphKo/MqSrWTnheyx/zKFM71B47qsZIGByCJ7OYRYUkUMDP+laz7uAf3f8e 9gT+fnOb3eZu3LlQFcgt0hnOjILC9N2ZDDhlrHDoTmIdK6wjl6VVxDFjmjDfqwNeOMcC NRjw== X-Gm-Message-State: AMCzsaW57fxMU2sHMUebEioO0KPSW61lmp6nwyce4VzqPvKq2x/UKmBl 4UEp5FHCBOk4SYnlSJHfvY7xEA== X-Google-Smtp-Source: ABhQp+S6cnGFgPL3AvSb+r/HBWhxD8X5dyORTI5gXNIKqUnE51PXpbyqaF2GcJ/qTcy+hOCo9bda0g== X-Received: by 10.46.91.138 with SMTP id m10mr2128603lje.95.1509520624055; Wed, 01 Nov 2017 00:17:04 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:45 +0100 Message-Id: <20171101071652.19375-7-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v6 06/13] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update striping functionality to be big-endian bit order (as according to the Zynq-7000 Technical Reference Manual). Output thereafter the even bits into the flash memory connected to the lower QSPI bus and the odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 559fa79..7accf5d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -208,14 +208,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): * - * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { 52hebGDA, }} */ =20 static inline void stripe8(uint8_t *x, int num, bool dir) @@ -223,15 +223,15 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] =3D {0, 0}; - int bit[2] =3D {0, 0}; + int bit[2] =3D {0, 7}; int d =3D dir; =20 for (idx[0] =3D 0; idx[0] < num; ++idx[0]) { - for (bit[0] =3D 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |=3D x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] =3D 7; bit[0] !=3D -1; bit[0] +=3D -1) { + r[idx[!d]] |=3D x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] =3D (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1] +=3D -1; } } } @@ -266,8 +266,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { + int bus =3D num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); } =20 --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150952076967530.466662895898935; Wed, 1 Nov 2017 00:19:29 -0700 (PDT) Received: from localhost ([::1]:48701 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nJ5-0007YB-5j for importer@patchew.org; Wed, 01 Nov 2017 03:19:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGw-0006DK-A4 for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGt-0001U1-FG for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:10 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:52019) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGt-0001Tl-4C for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:07 -0400 Received: by mail-lf0-x242.google.com with SMTP id r129so1470800lff.8 for ; Wed, 01 Nov 2017 00:17:07 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=ihenHRlF7/0+JhUSV6aCEWOOvwtpurDQDZ0B6Fxq+MSQ2iSlBPG/Ey/y14OhFbtHKt 2Kot6I1rE3c2eZJVGLe0GzhAyQA53X1HnJMIXqICM3xqm/E1RaJkiJ+nVXKZ/x8u+DH6 wmj0AxNTjwj8eGQfaLob8N4ICBfTxe73XW4ZgwhlviNjzfKch0GQ++3OjPXE10iscNto n6NkkptRzLw2zK+Lhdy2DCJw2TXhvbdf4+vIakYpXdCl3VXjzA3nz1XrfZBe4T9daBW6 OWEzwguaVdEM6xiWebCWEYTns9hLCcX+CR4H4TJlVNYPj+UEF519Al3sd7d8OrieJZuf dAAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=UenowhWVwTkK1sKEcxw40LCLxNhp3wWhf+Tq+OVOzxqpPgtDW9vzKGBVEtraaNO12o n0Tt2Uw4QSPPqpe5n0P3Nd6Ho8rRxA5TVRAxlOlvH/jJJyzm0nGME/LM4rUr2Okw83oA IQATRfmpLE4L6AmHcZhOGSOgoEv8+i4reuAy6ozFpixLjm0j9MSHyzSYQHHHZ0m2Z3bw GL4hGx8TYezV5GAnYvDwD3jD/XiZTcLEFLnFDVvI/FckoDnvbWYreuRBZ3ufMn2z4l3K avpp330l6eu2WB6XVsePvFOTx/UYhlpyNkMQlSpuz2ace9/SOOFNa7XUFsQnPGQl2X63 AkIQ== X-Gm-Message-State: AMCzsaVI3zHxnp8r9qbRLRftS6iZtlb1+go03bIQVabl3ZBmVu8AosKi 5xGMZ+r2e7jHlaGUpeLEG91Wow== X-Google-Smtp-Source: ABhQp+SAnmMC3J94baa4nx7paB3fTgaldfErR11Xvk+T2VPWk396kPeBDRgXSr/ASS7zrNuQNSp08w== X-Received: by 10.46.89.147 with SMTP id g19mr1973760ljf.26.1509520625533; Wed, 01 Nov 2017 00:17:05 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:46 +0100 Message-Id: <20171101071652.19375-8-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v6 07/13] xilinx_spips: Add support for RX discard and RX drain X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 167 +++++++++++++++++++++++++++++++++++++-= ---- include/hw/ssi/xilinx_spips.h | 6 ++ 2 files changed, 155 insertions(+), 18 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7accf5d..8634810 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -30,6 +30,7 @@ #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" +#include "hw/register.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -100,6 +101,14 @@ #define LQSPI_CFG_DUMMY_SHIFT 8 #define LQSPI_CFG_INST_CODE 0xFF =20 +#define R_CMND (0xc0 / 4) + #define R_CMND_RXFIFO_DRAIN (1 << 19) + FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) +#define R_CMND_EXT_ADD (1 << 15) + FIELD(CMND, RX_DISCARD, 8, 7) + FIELD(CMND, DUMMY_CYCLES, 2, 6) +#define R_CMND_DMA_EN (1 << 1) +#define R_CMND_PUSH_WAIT (1 << 0) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -116,7 +125,8 @@ #define LQSPI_ADDRESS_BITS 24 =20 #define SNOOP_CHECKING 0xFF -#define SNOOP_NONE 0xFE +#define SNOOP_ADDR 0xF0 +#define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 =20 static inline int num_effective_busses(XilinxSPIPS *s) @@ -146,9 +156,14 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT_L(0, "selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); + if (s->cs_lines_state[cs_to_set]) { + s->cs_lines_state[cs_to_set] =3D false; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); + } } else { DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); + s->cs_lines_state[cs_to_set] =3D true; } } if (xilinx_spips_cs_is_set(s, i, field)) { @@ -157,6 +172,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) } if (!found) { s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; DB_PRINT_L(1, "moving to snoop check state\n"); } } @@ -203,7 +222,11 @@ static void xilinx_spips_reset(DeviceState *d) /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] =3D 0x01090106; s->regs[R_LQSPI_CFG] =3D R_LQSPI_CFG_RESET; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -238,14 +261,69 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) +{ + if (!qs) { + /* The SPI device is not a QSPI device */ + return -1; + } + + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 5; + default: + return -1; + } +} + +static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) +{ + switch (cmd) { + case PP_4: + case QPP_4: + case READ_4: + case QIOR_4: + case FAST_READ_4: + case DOR_4: + case QOR_4: + case DIOR_4: + return 4; + default: + return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; + } +} + static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) { int debug_level =3D 0; + XilinxQSPIPS *q =3D (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), + TYPE_XILINX_QSP= IPS); =20 for (;;) { int i; uint8_t tx =3D 0; uint8_t tx_rx[num_effective_busses(s)]; + uint8_t dummy_cycles =3D 0; + uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { @@ -258,54 +336,102 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] =3D fifo8_pop(&s->tx_fifo); } stripe8(tx_rx, num_effective_busses(s), false); - } else { + } else if (s->snoop_state >=3D SNOOP_ADDR) { tx =3D fifo8_pop(&s->tx_fifo); for (i =3D 0; i < num_effective_busses(s); ++i) { tx_rx[i] =3D tx; } + } else { + /* Extract a dummy byte and generate dummy cycles according to= the + * link state */ + tx =3D fifo8_pop(&s->tx_fifo); + dummy_cycles =3D 8 / s->link_state; } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { int bus =3D num_effective_busses(s) - 1 - i; - DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); - DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + if (dummy_cycles) { + int d; + for (d =3D 0; d < dummy_cycles; ++d) { + tx_rx[0] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx= [0]); + } + } else { + DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); + DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + } } =20 - if (fifo8_is_full(&s->rx_fifo)) { + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); + /* Do nothing */ + } else if (s->rx_discard) { + DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); + s->rx_discard -=3D 8 / s->link_state; + } else if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_INTR_STATUS] |=3D IXR_RX_FIFO_OVERFLOW; DB_PRINT_L(0, "rx FIFO overflow"); } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { stripe8(tx_rx, num_effective_busses(s), true); for (i =3D 0; i < num_effective_busses(s); ++i) { fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); + DB_PRINT_L(debug_level, "pushing striped rx byte\n"); } } else { + DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); } =20 + if (s->link_state_next_when) { + s->link_state_next_when--; + if (!s->link_state_next_when) { + s->link_state =3D s->link_state_next; + } + } + DB_PRINT_L(debug_level, "initial snoop state: %x\n", (unsigned)s->snoop_state); switch (s->snoop_state) { case (SNOOP_CHECKING): - switch (tx) { /* new instruction code */ - case READ: /* 3 address bytes, no dummy bytes/cycles */ - case PP: + /* Store the count of dummy bytes in the txfifo */ + s->cmd_dummies =3D xilinx_spips_num_dummies(q, tx); + addr_length =3D get_addr_length(s, tx); + if (s->cmd_dummies < 0) { + s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D SNOOP_ADDR + addr_length - 1; + } + switch (tx) { case DPP: - case QPP: - s->snoop_state =3D 3; - break; - case FAST_READ: /* 3 address bytes, 1 dummy byte */ case DOR: + case DOR_4: + s->link_state_next =3D 2; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case QPP: + case QPP_4: case QOR: - case DIOR: /* FIXME: these vary between vendor - set to spansi= on */ - s->snoop_state =3D 4; + case QOR_4: + s->link_state_next =3D 4; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case DIOR: + case DIOR_4: + s->link_state =3D 2; break; - case QIOR: /* 3 address bytes, 2 dummy bytes */ - s->snoop_state =3D 6; + case QIOR: + case QIOR_4: + s->link_state =3D 4; break; - default: + } + break; + case (SNOOP_ADDR): + /* Address has been transmitted, transmit dummy cycles now if + * needed */ + if (s->cmd_dummies < 0) { s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D s->cmd_dummies; } break; case (SNOOP_STRIPING): @@ -483,6 +609,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, uint64_t value, unsigned size) { XilinxQSPIPS *q =3D XILINX_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(opaque); =20 xilinx_spips_write(opaque, addr, value, size); addr >>=3D 2; @@ -490,6 +617,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, if (addr =3D=3D R_LQSPI_CFG) { xilinx_qspips_invalidate_mmio_ptr(q); } + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + fifo8_reset(&s->rx_fifo); + } } =20 static const MemoryRegionOps qspips_ops =3D { @@ -632,6 +762,7 @@ static void xilinx_spips_realize(DeviceState *dev, Erro= r **errp) } =20 s->cs_lines =3D g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state =3D g_new0(bool, s->num_cs * s->num_busses); for (i =3D 0, cs =3D s->cs_lines; i < s->num_busses; ++i, cs +=3D s->n= um_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7f9e2fc..bac90a5 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -61,13 +61,19 @@ struct XilinxSPIPS { uint8_t num_busses; =20 uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; =20 Fifo8 rx_fifo; Fifo8 tx_fifo; =20 uint8_t num_txrx_bytes; + uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; }; --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 150952099286665.27393227003995; Wed, 1 Nov 2017 00:23:12 -0700 (PDT) Received: from localhost ([::1]:48719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nMd-00027O-3l for importer@patchew.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=arYd0JSEqRc0LGmEOqBIbXR2vigPRmtBWZID165j3tORqQwZPJagQXMc7OsEfCi9+w ir6+f6Mm7TbKl+GDAxk1mNvdPE5NS+yVaxlC8t56oGTj4IihJRGJ4vvqeD12RIAq42KI Wb0e/Ae2OsgZG/vHyipBvulD3UtdC8NO9EAbQkTJEyiB9rfu4adPKU6bkEby4ruDaJZ+ /XVFN4NUqZ9X2ieOurYdk69eGO8FDFJIdyjJD5dWsCL3Jjl02hOw1LM8ro406pWGK8BB 25nFbLasKSIuKuyzOsIAcMwDY4F163hAHFrGizrDPLe/OmsVxjWRQjEFSKwF0dfPBn+0 O7bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=ilMMLLJVUJZxfLm1y0rgOpgh8NAhgBBxhKufqKysIwcBQ7tkwvjxut25RfXP3jqJzA eK+Tz8vs4T8EKmY2lM2U7iGZ/qIClCgyxcpSyzOIDsVVsjQ9fW8I4goFx85zJv/ePtA9 C3jOVzjOPa7HflNfnKwRQn0nTBNoKDaXWc8BuBma/Ct5Ks//brgMFBk/ZgjVgLwJ0HDO fUY/vtZ58jpqtOh4RXIcotjVuOr8jvMEUPiS34L8M/NC+9cS38OkgmJ9UX56azAsNwYA 5bxc38EijSsS4H5EaA2ltoQiBD3UGWaVGILp12l5jv5hnCmK8qIaWKcFwDWc0V1Ga7rL 3f6A== X-Gm-Message-State: AMCzsaVqquzGQGa7byatjF++0besTt10zcQt5RjN7W9lGlVjdhOzsME6 aq5ZdbqGswSm3hYjvVK0t6ZFCw== X-Google-Smtp-Source: ABhQp+Qcw3te7k64EldJVl//fhVH31ZFW3Lp27J6SmitdQKBclIFtsImLCZ5u+kd9u4Y315+GlEGwg== X-Received: by 10.46.83.20 with SMTP id h20mr2106632ljb.144.1509520626872; Wed, 01 Nov 2017 00:17:06 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:47 +0100 Message-Id: <20171101071652.19375-9-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 64 +++++++++++++++++++++++++++++------------------= ---- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8634810..e37d005 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -450,13 +450,28 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } =20 -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, boo= l be) { int i; + for (i =3D 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<=3D 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>=3D 8; + } + } +} =20 - for (i =3D 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - value[i] =3D fifo8_pop(&s->rx_fifo); +static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) +{ + int i; + + for (i =3D 0; i < max && !fifo8_is_empty(fifo); ++i) { + value[i] =3D fifo8_pop(fifo); } + return max - i; } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -466,6 +481,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, uint32_t mask =3D ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; =20 addr >>=3D 2; switch (addr) { @@ -496,9 +512,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret =3D s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_b= uf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall =3D rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes= ); + ret =3D s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<=3D 8 * shortfall; + } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -509,20 +529,6 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i =3D 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<=3D 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>=3D 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -563,16 +569,20 @@ static void xilinx_spips_write(void *opaque, hwaddr a= ddr, mask =3D 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); @@ -682,11 +692,11 @@ static void lqspi_load_cache(void *opaque, hwaddr add= r) =20 while (cache_entry < LQSPI_CACHE_SIZE) { for (i =3D 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i =3D 0; i < 64; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); + rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1= ); } } =20 --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509521124405940.2714816852629; Wed, 1 Nov 2017 00:25:24 -0700 (PDT) Received: from localhost ([::1]:48727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nOp-0003wq-Hq for importer@patchew.org; Wed, 01 Nov 2017 03:25:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGx-0006E5-2R for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGv-0001V5-Uf for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:11 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:55910) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGv-0001Uf-N3 for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:09 -0400 Received: by mail-lf0-x241.google.com with SMTP id e143so1459414lfg.12 for ; Wed, 01 Nov 2017 00:17:09 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mCaEpfG3yh3OwFFZzRqwNotlNRit/2TIHL1vZNUSFRA=; b=JztJhC1+9z4U9g6h2Vm62NsVICGYRRznBWXZiMaHdzUACptRn1bB/FYsP4hMn+SMDN fkFdDqS83UxSZhusA7gsZpAXeueWvjvOLMNvcZak2q7A+AreipLWzhg4iYmojSXnqQCn N6Q5D93g5fivGWxuBuBfT+7qSKAjB/sQpuQl5k80aA3V7VAl7AwIMuNaYYz9r175rl3M pVg1AawLSZAu+iTppmhyXGLnT4xqHHhIT9DEl8qBwqDTeXmNd+NvUzuDXRkBp+4SpqST KhSFqrJQqTNyqHBIbgnOEMVbpVoQ2olnIfJJOqGEaxO3SssTBRYQjwQgRWsvyZsmPLBr l5qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mCaEpfG3yh3OwFFZzRqwNotlNRit/2TIHL1vZNUSFRA=; b=DeThOlB5BjqS97J+oRwQdqiW/28dvbKgpcEVLOgEeaO14V5hq0ih4nPP/Vb33I61Ef Tm02VGL0rXXN4gfcuVsoFlXrOb4T02dU/LwATYICdoSGtC2qXZqoIX/jdUZYxA1m4K1U cDCsLgS44DXLn9Qf2TNwyNkVwivcvX62vk0Dc0LzH+X2R+/DOkEmzZlpcZfshexVgdu5 Sc5MDTr8eEcGHGzQ0qtcWvOVsKn3k3aKhB7NSsCfV4+kfyrrn41NM6+kGKWCyu+XmcJL XpTIZ7mhMzNKSOjC7Uc64pegQy26K5w6dkpYEirutNP5ojiVGlB9tk7h5fH8xUcr5iXN K9cg== X-Gm-Message-State: AMCzsaX7mUcvkTiU9zRHe3ymBeKSNw60FCQzrEINf2YYswSzA0doJ0zA InZm+fqhzAwGw3Q4Bg8QDa6KKA== X-Google-Smtp-Source: ABhQp+Q3mcLVosqukJAXBXtvRzqQ9+LdOY/BzBCyHGBhQYjBEO8IKKkxMRyybQY+msuXYEzb3XawIQ== X-Received: by 10.46.68.73 with SMTP id r70mr2071556lja.174.1509520628247; Wed, 01 Nov 2017 00:17:08 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:48 +0100 Message-Id: <20171101071652.19375-10-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v6 09/13] xilinx_spips: Add support for zero pumping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++---= ---- include/hw/ssi/xilinx_spips.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e37d005..3a98799 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ FIELD(CMND, DUMMY_CYCLES, 2, 6) #define R_CMND_DMA_EN (1 << 1) #define R_CMND_PUSH_WAIT (1 << 0) +#define R_TRANSFER_SIZE (0xc4 / 4) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d) s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; + s->man_start_com =3D false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t= value, int num, bool be) } } =20 +static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) +{ + if (!s->regs[R_TRANSFER_SIZE]) { + return; + } + if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT= ) { + return; + } + /* + * The zero pump must never fill tx fifo such that rx overflow is + * possible + */ + while (s->regs[R_TRANSFER_SIZE] && + s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { + /* endianess just doesn't matter when zero pumping */ + tx_data_bytes(&s->tx_fifo, 0, 4, false); + s->regs[R_TRANSFER_SIZE] &=3D ~0x03ull; + s->regs[R_TRANSFER_SIZE] -=3D 4; + } +} + +static void xilinx_spips_check_flush(XilinxSPIPS *s) +{ + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } + if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { + s->man_start_com =3D false; + } + xilinx_spips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, uint64_t value, unsigned size) { int mask =3D ~0; - int man_start_com =3D 0; XilinxSPIPS *s =3D opaque; =20 DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); @@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, switch (addr) { case R_CONFIG: mask =3D ~(R_CONFIG_RSVD | MAN_START_COM); - if (value & MAN_START_COM) { - man_start_com =3D 1; + if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN))= { + s->man_start_com =3D true; } break; case R_INTR_STATUS: @@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr ad= dr, s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: xilinx_spips_update_cs_lines(s); - if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || - (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_= EN)) { - xilinx_spips_flush_txfifo(s); - } + xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index bac90a5..ad2175a 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -76,6 +76,8 @@ struct XilinxSPIPS { uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; =20 typedef struct { --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509520922268885.6117789280199; Wed, 1 Nov 2017 00:22:02 -0700 (PDT) Received: from localhost ([::1]:48716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nLZ-0001Ao-W2 for importer@patchew.org; Wed, 01 Nov 2017 03:21:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGy-0006EC-2P for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGx-0001Vl-5Y for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:12 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:44606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGw-0001VC-Uz for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:11 -0400 Received: by mail-lf0-x243.google.com with SMTP id 75so1491676lfx.1 for ; Wed, 01 Nov 2017 00:17:10 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9xWCi1U1MzTiqRRKJPWrpHbnKQEwWZwqcARbHEmA394=; b=XOEJvFzbNxLTgjyI9tTZFIJFIVijmhGjQ4oslppR9rJUtLZiDU7z4eVJiscALKdwvF FgeASY/wvvx8n4+gCMG8tWMF/jN7nutHFp7CP2/MTwqNvg8ghfFbgoYfd70Snb2o+8/3 I1BpH+NBv7huHTbWsdhtlwjUA4aWw/pk3dKJu1bVm3FxjEAczXL9Y17pwehf9VfaGKxd yhbp8PVnungoSz4pi0Mp2FVTfigSKjFTG074zJO1bZv+c5aqmmfuuij3LWhjS1u7jZ5m i7AecU4uCUGLPQ/m1xx9jlTN05/6Tddh/nwFBC2jVZZrN1Zgg2Z2ecidYM5iXTubyHup n13g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9xWCi1U1MzTiqRRKJPWrpHbnKQEwWZwqcARbHEmA394=; b=cGJ9u9FSojR9hS4zUUT5dG4jDC0cb/1irYPWVD35g3wEIHN75U/q95ZmdqnxvqyTv2 UVyBtULUApPmu4FDp7bUh804hv3EpXPcS1AiZcB04SW8OapWbwYFOD4NPf4au5wajBKD 4HSQWaaBssiAQ04X3jqqbM+dYs1OZCu/TKPI3N0Td0d+I445Sj0y8PR1ZMsskjQiWfs+ Ynq45Yi88b2mfxXQBtTPC0UfSRwciPfZbqXsGbNBxNRvW/WJ+FgyI2M4fC3c1d4F6EjJ etb4CsrWDImui40OkC7cd7X+jKzvjXwxqHc8v142l4vV+S/3f460MXT8UsHo0Mzt9JLk Otvg== X-Gm-Message-State: AMCzsaWfWlt5XlSWFBDBPKLuJHfOYse19qTYpJz3tSi9PpYP89jqnBsI EvrV4Hh5lfVjwoG4fWHEwGONxw== X-Google-Smtp-Source: ABhQp+QvV5ZT/uSLI3//J+omLhW/VNIH6dCHdPCYvl/E0L+nhuv5vq2tk9FFZa5aZrlO7HLDZ/nDgg== X-Received: by 10.25.33.139 with SMTP id h133mr1506421lfh.140.1509520629532; Wed, 01 Nov 2017 00:17:09 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:49 +0100 Message-Id: <20171101071652.19375-11-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 3a98799..7f0f317 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE= ); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509521081066949.3267390639245; Wed, 1 Nov 2017 00:24:41 -0700 (PDT) Received: from localhost ([::1]:48725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nNz-0003JO-RC for importer@patchew.org; Wed, 01 Nov 2017 03:24:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nGz-0006EE-BX for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nGy-0001WU-Fw for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:13 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:46665) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGy-0001W3-8O for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:12 -0400 Received: by mail-lf0-x244.google.com with SMTP id g70so1489829lfl.3 for ; Wed, 01 Nov 2017 00:17:12 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=Lvf9XXsKAWIdSABCivF6TpvHoRHssyl12EEcd4ZKraSjptiGydOyXZwQcyEpFRpSbD K7yFGjflzvzbhePfaRxXqAsPHM12kfO8+ItPvp9vdcvGYWPwU/ZpAX9SIFmYIc53e702 lBCEZFmzWu6Mef+J8WchEiajNUSXGDUe+CVSfQ/6+CGE8v7nu2RMCBn9AGxHlTER1dYP 7NsU2k9Un6bo+0Y9OfmzwX+Cq92/Myw7XD3bGNhGumIUo35T6ZnENd9sGfbbcxImdnDu 2E/vUskI37gQtmU6e7W4R7Kch0GU1OqM5ULXiws7xxncSzQvzHNQQknFvMKYu+v+byeF iqOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=P4tRRNgYUEZ5WYsLjsSf0Qdwj11o+QoC95Q49sE+DMtVOyAWd1yo7c0Phr0J3tHZeJ +U8XHFzqADDUlOFyk+9Die8ICm9sSrL6f/8u1bhAxv06J0+YR/llHNJdcrvTfvT3J8Uw LAdhL1SiXsl63oKoVsKFcYfaFAZg6ME1TCqv1TTmeK86DwOc3J24s1+zeDbQVDTiZDe2 KsTIvkrTFncl7eJzxfSnE8cNHyQrIoiuqvxGKycdzl2lOKyq+fNOVG0R5qbAQbnZaGjI NJ2IMqm8WgsV8b55EFNjdZlFlmjBerx2HO32CBGcruNiMjVMxDA3gY7oaQ6aKHZTR8Qr /nAQ== X-Gm-Message-State: AMCzsaVYRooGAygSVl6lZ631bt6M57Vlvd66KJ8vsHfqy7EfI3DPG+72 BL5eJr5yiuhbh2fm58ELOBgt6Q== X-Google-Smtp-Source: ABhQp+QsS8kPlF1O39EDii2J/LOrOeQHXpjnKA0n0/UzCJBhI0EjxUh8eGaravZnP+ns+H+zlDjHyA== X-Received: by 10.25.202.25 with SMTP id a25mr1825791lfg.83.1509520630760; Wed, 01 Nov 2017 00:17:10 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:50 +0100 Message-Id: <20171101071652.19375-12-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v6 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7f0f317..159a89d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |=3D IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, ret =3D s->regs[addr] & IXR_ALL; s->regs[addr] =3D 0; DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask =3D IXR_ALL; --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509521197588370.4177421207895; Wed, 1 Nov 2017 00:26:37 -0700 (PDT) Received: from localhost ([::1]:48736 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nPz-0004yG-Ku for importer@patchew.org; Wed, 01 Nov 2017 03:26:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nH3-0006JG-GT for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nH0-0001X9-Fp for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:17 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:47489) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nGz-0001Wi-Vf for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:14 -0400 Received: by mail-lf0-x243.google.com with SMTP id k40so1480878lfi.4 for ; Wed, 01 Nov 2017 00:17:13 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/izqVw15TY9loMzngzVBRcQ0x82kDHiWNTv8ns1FHPQ=; b=OgfAhEj/r0I+FIKNBbHKDBci6srZUNoW6MGRBg1KCVQtJ0zU0N96dV88LQUr/rjBHg w6M9AolRTgiv2vQa/H5hjsEPCTGMw6XQ/5zSHc1OTzIxJ3FG55b5wuFni2btzNDeuVIo vVod6M6XbEhtyrH6uqu7K/nI93O/lGBJNV/JFlv0FvmGX6ElB/Du9CYVXpflsNFHg4Vd Dn0eXGXx4u/oGzAwDKkQIZlachZGeU4VibXbxAJulqcm3jrRzZW+iOtfyTDgZG+mTROb 9EAiNf1tnn3wRWEcmZmrmcjbjDjnpKKYXyfftOA7KHJaY2jTsjTK420u+U5dS7nUmQQa Fd8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/izqVw15TY9loMzngzVBRcQ0x82kDHiWNTv8ns1FHPQ=; b=fPlrLxFYC6q/AR9JypQO0lFf0AD5gjiH0AivRvhqgjfCPBzc2LIn8LwUgG0h/tYJV8 i6y+pBih6lKQgt+4Ny6asM9vziez1JDBqulNxNarHXt0dNfYBBvt1bZi6J9d8Gt3LdcS PRnFc3KZ7L4cNIieiunZOUQ4GlSW4RE7+OpBw1+UeZdpC7P7hff0R6zKnDmJzpuSIIms FWgf+OYSpvvi9DC2hD2UN9nblQEa+9ZYULUUbhMmc+rCjCvYeumTtR5VskYWxCH7YuN4 EQet918o/nTvh1DOwAqcYwrOMXrmDW5WfJSrv66u+MvAr9pYzXqUcrklauTsTGcxbVn9 Wb3Q== X-Gm-Message-State: AMCzsaWNX5JS1SfOvnI//ly4a0cOFL3ASFSDiLHhLqovO/VyT2jRfXO+ Lj+O9rfzNobomwBuTqlQnbpdhw== X-Google-Smtp-Source: ABhQp+Rzlqt2tQvLmjzJpvNB8UiWyfp6sCtGOkPA1UBCGAVbfW5RK7+uHW+G7W7sgy4NlR6ynTqpjQ== X-Received: by 10.25.153.136 with SMTP id b130mr1712850lfe.233.1509520632183; Wed, 01 Nov 2017 00:17:12 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:51 +0100 Message-Id: <20171101071652.19375-13-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v6 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias --- default-configs/arm-softmmu.mak | 1 + hw/ssi/xilinx_spips.c | 574 ++++++++++++++++++++++++++++++++++++= ---- include/hw/ssi/xilinx_spips.h | 32 ++- 3 files changed, 559 insertions(+), 48 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 5059d13..d09fd34 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,3 +130,4 @@ CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy CONFIG_MSF2=3Dy +CONFIG_XILINX_AXI=3Dy diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 159a89d..938064d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,30 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) =20 #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -116,9 +134,54 @@ =20 #define R_MOD_ID (0xFC / 4) =20 +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) +#define R_GQSPI_GEN_FIFO (0x140 / 4) +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) +#define R_GQSPI_DATA_STS (0x15c / 4) +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) =20 #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -137,42 +200,22 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } =20 -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) -{ - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); -} - -static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) { - int i, j; - bool found =3D false; - int field =3D s->regs[R_CONFIG] >> CS_SHIFT; + int i; =20 for (i =3D 0; i < s->num_cs; i++) { - for (j =3D 0; j < num_effective_busses(s); j++) { - int upage =3D !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set =3D (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - if (s->cs_lines_state[cs_to_set]) { - s->cs_lines_state[cs_to_set] =3D false; - s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); - } - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - s->cs_lines_state[cs_to_set] =3D true; - } - } - if (xilinx_spips_cs_is_set(s, i, field)) { - found =3D true; + bool old_state =3D s->cs_lines_state[i]; + bool new_state =3D field & (1 << i); + + if (old_state !=3D new_state) { + s->cs_lines_state[i] =3D new_state; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de",= i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; s->link_state =3D 1; @@ -182,21 +225,51 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS = *s) } } =20 +static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) +{ + if (s->regs[R_GQSPI_GF_SNAPSHOT]) { + int field =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SE= LECT); + xilinx_spips_update_cs(XILINX_SPIPS(s), field); + } +} + +static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +{ + int field =3D ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) =3D=3D 2) { + /* Single bit chip-select for qspi */ + field &=3D 0x1; + field |=3D field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + field &=3D 0x1; + /* change from CS0 to CS1 */ + field <<=3D 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + field =3D 0; + } + xilinx_spips_update_cs(s, field); +} + static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &=3D ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |=3D + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL := 0); } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &=3D (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERF= LOW | - IXR_TX_FIFO_MODE_FAIL); - /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |=3D - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY := 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); - /* drive external interrupt pin */ int new_irqline =3D !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & IXR_ALL); if (new_irqline !=3D s->irqline) { @@ -205,6 +278,39 @@ static void xilinx_spips_update_ixr(XilinxSPIPS *s) } } =20 +static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) +{ + uint32_t gqspi_int; + int new_irqline; + + s->regs[R_GQSPI_ISR] &=3D ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |=3D + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >=3D s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + /* GQSPI Interrupt Trigger Status */ + gqspi_int =3D (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_I= XR_MASK; + new_irqline =3D !!(gqspi_int & IXR_ALL); + + /* drive external interrupt pin */ + if (new_irqline !=3D s->gqspi_irqline) { + s->gqspi_irqline =3D new_irqline; + qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); + } else { + xilinx_spips_update_ixr(XILINX_SPIPS(s)); + } +} + static void xilinx_spips_reset(DeviceState *d) { XilinxSPIPS *s =3D XILINX_SPIPS(d); @@ -234,6 +340,27 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 +static void xlnx_zynqmp_qspips_reset(DeviceState *d) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(d); + int i; + + xilinx_spips_reset(d); + + for (i =3D 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) { + s->regs[i] =3D 0; + } + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); + s->regs[R_GQSPI_TX_THRESH] =3D 1; + s->regs[R_GQSPI_RX_THRESH] =3D 1; + s->regs[R_GQSPI_GFIFO_THRESH] =3D 1; + s->regs[R_GQSPI_IMR] =3D GQSPI_IXR_MASK; + s->man_start_com_g =3D false; + xlnx_zynqmp_qspips_update_ixr(s); +} + /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: @@ -264,6 +391,108 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2] =3D { 0 }; + int num_stripes =3D 1; + uint8_t busses; + int i; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] =3D fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSH= OT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing= "); + continue; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + + imm =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE= _DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)= || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))= { + s->regs[R_GQSPI_DATA_STS] =3D 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] =3D 0; + } + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONE= NT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer to= o" + " long - 2 ^ %" PRId8 " requested\n", im= m); + } + s->regs[R_GQSPI_DATA_STS] =3D 1ul << imm; + } else { + s->regs[R_GQSPI_DATA_STS] =3D imm; + } + } + /* Zero length transfer check */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && + (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { + num_stripes =3D 2; + } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] =3D ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT))= { + for (i =3D 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] =3D fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes =3D=3D 1) { + /* mirror */ + tx_rx[1] =3D tx_rx[0]; + } + busses =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_S= ELECT); + for (i =3D 0; i < 2; ++i) { + DB_PRINT_L(1, "bus %d tx =3D %02x\n", i, tx_rx[i]); + tx_rx[i] =3D ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); + DB_PRINT_L(1, "bus %d rx =3D %02x\n", i, tx_rx[i]); + } + if (s->regs[R_GQSPI_DATA_STS] > 1 && + busses =3D=3D 0x3 && num_stripes =3D=3D 2) { + s->regs[R_GQSPI_DATA_STS] -=3D 2; + } else if (s->regs[R_GQSPI_DATA_STS] > 0) { + s->regs[R_GQSPI_DATA_STS]--; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i =3D 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte =3D %02x\n", i, tx_rx[= i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -499,6 +728,25 @@ static void xilinx_spips_check_flush(XilinxSPIPS *s) xilinx_spips_update_ixr(s); } =20 +static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) +{ + bool gqspi_has_work =3D s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)))= { + xlnx_zynqmp_qspips_flush_fifo_g(s); + } + } else { + xilinx_spips_check_flush(XILINX_SPIPS(s)); + } + if (!gqspi_has_work) { + s->man_start_com_g =3D false; + } + xlnx_zynqmp_qspips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -509,6 +757,53 @@ static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *= value, int max) return max - i; } =20 +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max =3D=3D 0 || max > fifo->num) { + abort(); + } + *num =3D MIN(fifo->capacity - fifo->head, max); + ret =3D &fifo->data[fifo->head]; + fifo->head +=3D *num; + fifo->head %=3D fifo->capacity; + fifo->num -=3D *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) =3D=3D 2)) { + return; + } + recv_fifo =3D &rq->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo =3D &s->rx_fifo; + } + while (recv_fifo->num >=3D 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd =3D pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret =3D stream_push(rq->dma, rq->dma_buf, 4); + assert(ret =3D=3D 4); + xlnx_zynqmp_qspips_check_flush(rq); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -556,6 +851,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, ret <<=3D 8 * shortfall; } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -565,6 +861,43 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 +static uint64_t xlnx_zynqmp_qspips_read(void *opaque, + hwaddr addr, unsigned size) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg =3D addr / 4; + uint32_t ret; + uint8_t rx_buf[4]; + int shortfall; + + if (reg <=3D R_MOD_ID) { + return xilinx_spips_read(opaque, addr, size); + } else { + switch (reg) { + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Read from empty GQSPI RX FIFO\n"); + return 0; + } + memset(rx_buf, 0, sizeof(rx_buf)); + shortfall =3D rx_data_bytes(&s->rx_fifo_g, rx_buf, + XILINX_SPIPS(s)->num_txrx_bytes); + ret =3D ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { + ret <<=3D 8 * shortfall; + } + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_ixr(s); + return ret; + default: + return s->regs[reg]; + } + } +} + static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -664,12 +997,81 @@ static void xilinx_qspips_write(void *opaque, hwaddr = addr, } } =20 +static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg =3D addr / 4; + + if (reg <=3D R_MOD_ID) { + xilinx_qspips_write(opaque, addr, value, size); + } else { + switch (reg) { + case R_GQSPI_CNFG: + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)= ) { + s->man_start_com_g =3D true; + } + s->regs[reg] =3D value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + break; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + break; + case R_GQSPI_FIFO_CTRL: + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |=3D value; + break; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &=3D ~value; + break; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &=3D ~value; + break; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + break; + default: + s->regs[reg] =3D value; + break; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_update_ixr(s); + } + xlnx_zynqmp_qspips_notify(s); +} + static const MemoryRegionOps qspips_ops =3D { .read =3D xilinx_spips_read, .write =3D xilinx_qspips_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static const MemoryRegionOps xlnx_zynqmp_qspips_ops =3D { + .read =3D xlnx_zynqmp_qspips_read, + .write =3D xlnx_zynqmp_qspips_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 =20 static void lqspi_load_cache(void *opaque, hwaddr addr) @@ -818,7 +1220,7 @@ static void xilinx_spips_realize(DeviceState *dev, Err= or **errp) } =20 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, - "spi", XLNX_SPIPS_R_MAX * 4); + "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); sysbus_init_mmio(sbd, &s->iomem); =20 s->irqline =3D -1; @@ -856,6 +1258,28 @@ static void xilinx_qspips_realize(DeviceState *dev, E= rror **errp) } } =20 +static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(dev); + XilinxSPIPSClass *xsc =3D XILINX_SPIPS_GET_CLASS(s); + + xilinx_qspips_realize(dev, errp); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); +} + +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAV= E, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -877,6 +1301,40 @@ static const VMStateDescription vmstate_xilinx_spips = =3D { } }; =20 +static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) +{ + xlnx_zynqmp_qspips_update_ixr((XlnxZynqMPQSPIPS *)opaque); + xlnx_zynqmp_qspips_update_cs_lines((XlnxZynqMPQSPIPS *)opaque); + return 0; +} + +static const VMStateDescription vmstate_xilinx_qspips =3D { + .name =3D "xilinx_qspips", + .version_id =3D 2, + .minimum_version_id =3D 2, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, + vmstate_xilinx_spips, XilinxSPIPS), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_xlnx_zynqmp_qspips =3D { + .name =3D "xlnx_zynqmp_qspips", + .version_id =3D 2, + .minimum_version_id =3D 2, + .post_load =3D xlnx_zynqmp_qspips_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, + vmstate_xilinx_qspips, XilinxQSPIPS), + VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_M= AX), + VMSTATE_END_OF_LIST() + } +}; + static Property xilinx_qspips_properties[] =3D { /* We had to turn this off for 2.10 as it is not compatible with migra= tion. * It can be enabled but will prevent the device to be migrated. @@ -921,6 +1379,19 @@ static void xilinx_spips_class_init(ObjectClass *klas= s, void *data) xsc->tx_fifo_size =3D TXFF_A; } =20 +static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + XilinxSPIPSClass *xsc =3D XILINX_SPIPS_CLASS(klass); + + dc->realize =3D xlnx_zynqmp_qspips_realize; + dc->reset =3D xlnx_zynqmp_qspips_reset; + dc->vmsd =3D &vmstate_xlnx_zynqmp_qspips; + xsc->reg_ops =3D &xlnx_zynqmp_qspips_ops; + xsc->rx_fifo_size =3D RXFF_A_Q; + xsc->tx_fifo_size =3D TXFF_A_Q; +} + static const TypeInfo xilinx_spips_info =3D { .name =3D TYPE_XILINX_SPIPS, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -936,10 +1407,19 @@ static const TypeInfo xilinx_qspips_info =3D { .class_init =3D xilinx_qspips_class_init, }; =20 +static const TypeInfo xlnx_zynqmp_qspips_info =3D { + .name =3D TYPE_XLNX_ZYNQMP_QSPIPS, + .parent =3D TYPE_XILINX_QSPIPS, + .instance_size =3D sizeof(XlnxZynqMPQSPIPS), + .instance_init =3D xlnx_zynqmp_qspips_init, + .class_init =3D xlnx_zynqmp_qspips_class_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } =20 type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index ad2175a..9252069 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,13 @@ #define XILINX_SPIPS_H =20 #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" =20 typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) =20 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -89,6 +91,30 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; =20 +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; + int gqspi_irqline; + + uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; + + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * at the end of each generic command, misaligned extra bytes are disc= ard + * or padded to tx and rx respectively to round it out (and avoid need= for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; + bool man_start_com_g; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; =20 @@ -100,6 +126,7 @@ typedef struct XilinxSPIPSClass { =20 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" =20 #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -111,4 +138,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) =20 +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ --=20 2.9.3 From nobody Sun May 5 19:47:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150952093713912.859357484879183; Wed, 1 Nov 2017 00:22:17 -0700 (PDT) Received: from localhost ([::1]:48717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nLs-0001PL-9y for importer@patchew.org; Wed, 01 Nov 2017 03:22:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54560) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9nH2-0006IE-CA for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9nH1-0001XN-DD for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:16 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:52020) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9nH1-0001X3-1u for qemu-devel@nongnu.org; Wed, 01 Nov 2017 03:17:15 -0400 Received: by mail-lf0-x244.google.com with SMTP id r129so1471137lff.8 for ; Wed, 01 Nov 2017 00:17:14 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id c132sm562371lfe.37.2017.11.01.00.17.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Nov 2017 00:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=HDtFOpoHY7PiGycAMqhM1CvYU46gDZzKnknImhRYxXfUXdTNdHQxApzLZvKESVBOEf 7afaYZbiPxE94nvH+8BqFq1xZ0wE7iJB9f9KKnkxY8T4truFl3ttn85DrVvkbeklfUAS uELpMHeCKUByy93U1UmCJi8KNR5eRIkxBIYoR0asWzosbS8ETHmQuIk2ebNtjrz3QIpm LftjB5rfGh8faygQIAQ9kH9/ut55SZ3dDiQ19GkOEHIcpTvjKF9QZk1SrLDiatomjmYd aa25g4lT9oD91ja2zdTLuxFbSbKlfaO6WGWC099VRAb+JT9xksOOcdDvUMKzNwllzyiX ZGHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=cKEbU2az0wjCf913FtXaZIwPFqZgA12TTiuZOzxQ1kMr4V9HxOhv05x/o3eGrQptao PwKh/MFmvYagEvTDVPICg0F3h7bAZGB4DwSaGZkKElx7wtanqoboUAyQEXhHuel0C+aV gM5bZ91iM8hRwMfeRCnqzOvbEIqrPk1ir/5g9gja94sMUTjVUaT9a3MRa2/3IEOj/b3y AGdDhr3aAB5zHYFerba42QxCrFCS+PsXPQj3Ih8YwL0Qa/O22tcS6cfa+J1C62rPNjM9 huzKfSVJ8oPb7OeNFoL49EN82UJSKeTlNlIQR30quNHpwwLYPpo3ptzuoJs8d414imjS NeDA== X-Gm-Message-State: AMCzsaX/rKmBuHj9Z5kbAEg5YclxJETFMTlteU3GTl9Pi8Ol6zuBri31 bidtMaEzFAn4DhUagA+T4FytrA== X-Google-Smtp-Source: ABhQp+SgRQcgTJZ/sKGQh7q38eJ2JcZHWZ8wxMJPoFIwIV+VQ440w1AVrrNKJlKlUyO/q1FJeWoenA== X-Received: by 10.25.79.18 with SMTP id d18mr1632549lfb.246.1509520633518; Wed, 01 Nov 2017 00:17:13 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Wed, 1 Nov 2017 08:16:52 +0100 Message-Id: <20171101071652.19375-14-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171101071652.19375-1-frasse.iglesias@gmail.com> References: <20171101071652.19375-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v6 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 54 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..7d61972 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -150,6 +150,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineSta= te *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + int bus =3D i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name =3D g_strdup_printf("qspi%d", bus); + + spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name= ); + g_free(bus_name); + + flash_dev =3D ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(di= nfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ =20 xlnx_zcu102_binfo.ram_size =3D ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..46ac45d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 =20 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 =20 @@ -169,6 +173,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } =20 + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); =20 @@ -405,6 +412,25 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) g_free(bus_name); } =20 + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + + /* Alias controller SPI bus to the SoC itself */ + bus_name =3D g_strdup_printf("qspi%d", i); + target_bus =3D g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 =20 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; =20 --=20 2.9.3