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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=iwc83IRBxjgNnWO7Cf8oMK2CKiYcX13jzeGVotgQk1y8knVWBMawHlgO1G+8oisDTO 2j1xL4DFYL9GWVKdHisa5BP2zzi+HorKkxgyJRLuWISPs2pXqS50VjU1EHFzyKtIPxoz zOCEqHYPnSJkdg7JaFlvg6rNrtNMH34RKXmNqXi/XRd5cw1ADhwlE4dpEQ1TxP+0H1K4 4WEikbeuEGNQB3UcLLRHxGlXkRSac1K1aQdX9hFOCqpPlGVah27t4dVRb4LOpTIkRz7V Yik+c613KW+axWZF5azS1Q0CFUFx1ZRkWAOoyP4c2LYJV2UW86B6pdN5qdh95Nr3ctN4 DGQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=QgouMF/18OsbOqb2LK9iCD658RvJkPCplllMULzYNYUSu9FBUgtbUsInARtj4jKScw PU0b83ZoYcibc4RISk1YVO+vCpRMoMbTVSiEiwje9xEm73iSv1BvCB9L42lcLPQPUP7c dGW87Gp6uhOcUWADDzQIA7nKIVmcT5hLb2HsCCiTC/cE8UUHobYIzWhEVw8hpW8Fk8V/ 4zugzx6Ikn/gRKrjAhqC/roZ9M/0yT9fxx8fWLuiK1DOOHlQUL7N9k9031DAvzwhQStH tR043lsnEzx+B1Ne443xQ45KMr0DYLpbBZO+QmA9guU2ncfWkjHpaZJ88mTFPkWzCraD TiNA== X-Gm-Message-State: AMCzsaWpIy6aKcbmlg+drs9/cpUdQA+RbEE7vj5RNFeetyrLjVZlbVp3 lYt0rHtpdSnsryE/cPxGeL1g8Q== X-Google-Smtp-Source: ABhQp+Sbp/wM5SypvJnp/9rNZc8kTlyIHbGqDrjwbXlfdGpfNrPTwwrQTOJxmqeL9zrcUy91L+Qxvg== X-Received: by 10.25.78.10 with SMTP id c10mr1940912lfb.4.1509272038827; Sun, 29 Oct 2017 03:13:58 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:38 +0100 Message-Id: <20171029101343.15544-9-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v5 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 64 +++++++++++++++++++++++++++++------------------= ---- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8634810..e37d005 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -450,13 +450,28 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } =20 -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, boo= l be) { int i; + for (i =3D 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<=3D 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>=3D 8; + } + } +} =20 - for (i =3D 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - value[i] =3D fifo8_pop(&s->rx_fifo); +static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) +{ + int i; + + for (i =3D 0; i < max && !fifo8_is_empty(fifo); ++i) { + value[i] =3D fifo8_pop(fifo); } + return max - i; } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -466,6 +481,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, uint32_t mask =3D ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; =20 addr >>=3D 2; switch (addr) { @@ -496,9 +512,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret =3D s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_b= uf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall =3D rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes= ); + ret =3D s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<=3D 8 * shortfall; + } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -509,20 +529,6 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i =3D 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<=3D 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>=3D 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -563,16 +569,20 @@ static void xilinx_spips_write(void *opaque, hwaddr a= ddr, mask =3D 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); @@ -682,11 +692,11 @@ static void lqspi_load_cache(void *opaque, hwaddr add= r) =20 while (cache_entry < LQSPI_CACHE_SIZE) { for (i =3D 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i =3D 0; i < 64; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); + rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1= ); } } =20 --=20 2.9.3