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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.14.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:14:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=th4uT52S3Dis2XFnd+QH4dKbM9LQYmTZqjOIEVgwN1SRGjKrHjHYne5Za/cEIZPrPd Z9nYv5tyV113OZk/OPeRQ7o2iw6xmGWlGmHRCxlp25n1vuFvdoZBBHlG8b+rE0YxJwi2 /8p2toyI/lUv7sBHP4BKwArakI3vq8UtS0ci+tc8ECDkoO1gDI97wk3yrLELOKgDoLxa yr2HbSHPSm/lS+cJhkzyw7ZXGjqnTv49AnKiRhtZmziJpyHtKv7wLP+vD9yMbyovOo05 PDg+CMsOwRTigaj5ZVKMWGMNU354ni9WZo81m6jf1J8CbH5GtU/i9BOlakIhHYZrjuxB 88Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=Fal58jo1Z3Ls1/1EWn0Z5yf9PhaieWSicVKuXJFaXpZPWzGWCgNFb/lFLYM0YpoSSF mYYWKXyUan8mWKTxFt/GHmF7SBmczqqQdxQPiD9AynBshZLxvZU9KieIQUfH2oSniv7c 1Y98Itwb05Im6uugmYNqBRYULCrJY7xlVZ5eJ3H2yJ3U7YAHhyuHVWKWetAp0Sniyngy T2hc1tSL6kLgJHuEImDHTQL0TvC2FA5p7QmePrv88emOBYbdPNdj0Ro88R43zxRhf/PC LS1FKdSVjAk8Z9qqzgrSyPBw72f86rpePVeihuQy8If6/LIa3URSnwGNJDbdAjmbQeWp QUEw== X-Gm-Message-State: AMCzsaXQVyL/uiSV4ecoRPNeQdAtIXxx/0eSgFN5f9F31xR1oSy8nZfR ZQ0ecjbL7H9YSrcF6v0SWauAuA== X-Google-Smtp-Source: ABhQp+R0wdm2Kx7ldmebWxOcohmzRAUmzHgG6JkUFoC4S0dYmVvO9ixoYh+Onr5snkGFROMNKSu68w== X-Received: by 10.46.33.86 with SMTP id h83mr2335880ljh.193.1509272045711; Sun, 29 Oct 2017 03:14:05 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:43 +0100 Message-Id: <20171029101343.15544-14-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v5 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 54 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..7d61972 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -150,6 +150,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineSta= te *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + int bus =3D i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name =3D g_strdup_printf("qspi%d", bus); + + spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name= ); + g_free(bus_name); + + flash_dev =3D ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(di= nfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ =20 xlnx_zcu102_binfo.ram_size =3D ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..46ac45d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 =20 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 =20 @@ -169,6 +173,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } =20 + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); =20 @@ -405,6 +412,25 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) g_free(bus_name); } =20 + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + + /* Alias controller SPI bus to the SoC itself */ + bus_name =3D g_strdup_printf("qspi%d", i); + target_bus =3D g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 =20 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; =20 --=20 2.9.3