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X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v4 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice, Eon and Macronix. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Acked-by: Alistair Francis --- hw/block/m25p80.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a2438b9..2971519 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -423,6 +423,7 @@ typedef struct Flash { uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; uint32_t len; uint32_t pos; + bool data_read_loop; uint8_t needed_bytes; uint8_t cmd_in_progress; uint32_t cur_addr; @@ -983,6 +984,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -993,6 +995,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos =3D 0; s->len =3D 1; + s->data_read_loop =3D true; s->state =3D STATE_READING_DATA; break; =20 @@ -1133,6 +1136,7 @@ static int m25p80_cs(SSISlave *ss, bool select) s->pos =3D 0; s->state =3D STATE_IDLE; flash_sync_dirty(s, -1); + s->data_read_loop =3D false; } =20 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); @@ -1198,7 +1202,9 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32= _t tx) s->pos++; if (s->pos =3D=3D s->len) { s->pos =3D 0; - s->state =3D STATE_IDLE; + if (!s->data_read_loop) { + s->state =3D STATE_IDLE; + } } break; =20 --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084070977837.4612860382208; Thu, 26 Oct 2017 23:01:10 -0700 (PDT) Received: from localhost ([::1]:55865 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xhN-0000Of-4L for importer@patchew.org; Fri, 27 Oct 2017 02:00:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xd0-0005Y1-2B for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xcz-0007ki-B3 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:22 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:50168) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xcz-0007jf-3d for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:21 -0400 Received: by mail-lf0-x243.google.com with SMTP id w21so6148550lfc.6 for ; Thu, 26 Oct 2017 22:56:20 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TJfUvfz4QvqHP9eSJWPcWjAz0zl0Cv4oeE08DcRPD6Y=; b=ikuuUYuGNX0NWpR8MMVmramho5McZKAHRmKePUF97aUi/Sqlgu/MemNPIGqhsgeTHL LEPuLY7Emc9ZHIy9qTrBU89r3UP+PRgGHybSdgyynFHPXq1fUuTy1ZkJrWIMFR+k78c8 RodRbrR3G+C6NnlElGyr4/OWsRF+/AEDIRLRPoWFYnAL7/k58d6kr1nieKHXSZaUZGXU NxMbM4+4IYC5b7WGFkcAEPTidntq/8+vf1K7tsSu+Z935XpMWi7249/9u+uZBwWO4SE2 X9eNjTSgj+S2cIHT46TpG43al+bvE7KqCdJjHQ4o0aLgGZsyLAoAmlOEIEFlCUMX3ixw zIUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TJfUvfz4QvqHP9eSJWPcWjAz0zl0Cv4oeE08DcRPD6Y=; b=ncdx65ccRbN4038D2MuzwPD4c9X82U+M+4QcxKJ5RW7A4RQLNSWkQEPI7W0J6bLngv ySuGo6F/B7TsSZ1g6woqKcY7EZUA/2mlh0hqMMCRUA2oVn9R55tgjUfhQRJkLXtlw6Dj bBvSpdPg94eUVIlHC8TjNe9UCUwqt7L8ISa71falZopYHvOdk697tjRLRXSErtbu2S6S PAUZR3Qal3/kpsO4IPnmIhiJqAfxS9ITOBPtwtAm4oZ07B3vXmye0v2e9qeApQPph5+/ Cb+F9PBdDzh6woSolktgvMAVZfq3DuKfDcIx66sZq9HAYTcoufvwwH3tG1njNwxU/Bkb ATDg== X-Gm-Message-State: AMCzsaXbcpONoOQc0gGEhtBOqbc20JLwfLLWu68epJQ/FHZqbhIa4O4B 8UGOOZq3x03fOimUSMmM9wLiBVox X-Google-Smtp-Source: ABhQp+RdpYAkseHpE2yi05riYa1yVq8jCtgaSVnfbCsj2JhwHbz1TqF4GS0SOUWDk1Ic+pyy6MN8zA== X-Received: by 10.46.68.6 with SMTP id r6mr11068345lja.1.1509083779442; Thu, 26 Oct 2017 22:56:19 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:01 +0200 Message-Id: <20171027055612.2488-3-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis --- hw/block/m25p80.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 2971519..7a5c137 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -355,6 +355,8 @@ typedef enum { DPP =3D 0xa2, QPP =3D 0x32, QPP_4 =3D 0x34, + RDID_90 =3D 0x90, + RDID_AB =3D 0xab, =20 ERASE_4K =3D 0x20, ERASE4_4K =3D 0x21, @@ -405,6 +407,7 @@ typedef enum { MAN_MACRONIX, MAN_NUMONYX, MAN_WINBOND, + MAN_SST, MAN_GENERIC, } Manufacturer; =20 @@ -476,6 +479,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_SPANSION; case 0xC2: return MAN_MACRONIX; + case 0xBF: + return MAN_SST; default: return MAN_GENERIC; } @@ -711,6 +716,22 @@ static void complete_collecting_data(Flash *s) case WEVCR: s->enh_volatile_cfg =3D s->data[0]; break; + case RDID_90: + case RDID_AB: + if (get_man(s) =3D=3D MAN_SST && s->cur_addr <=3D 1) { + if (s->cur_addr) { + s->data[0] =3D s->pi->id[2]; + s->data[1] =3D s->pi->id[0]; + } else { + s->data[0] =3D s->pi->id[0]; + s->data[1] =3D s->pi->id[2]; + } + s->pos =3D 0; + s->len =3D 2; + s->data_read_loop =3D true; + s->state =3D STATE_READING_DATA; + } + break; default: break; } @@ -926,6 +947,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) case PP4: case PP4_4: case DIE_ERASE: + case RDID_90: + case RDID_AB: s->needed_bytes =3D get_addr_length(s); s->pos =3D 0; s->len =3D 0; --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 150908392554476.23684212677392; Thu, 26 Oct 2017 22:58:45 -0700 (PDT) Received: from localhost ([::1]:55854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xf1-0006q2-DT for importer@patchew.org; Fri, 27 Oct 2017 01:58:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50686) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xd1-0005YB-D5 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xd0-0007m1-Ky for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:23 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:54225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xd0-0007ks-DJ for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:22 -0400 Received: by mail-lf0-x244.google.com with SMTP id l23so6114319lfk.10 for ; Thu, 26 Oct 2017 22:56:22 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vrR3H5hGfnA2aTla5ccrl66sGlVMe3bSdnKTzLO2pcE=; b=cGe+HgX0q5CNm5THdEIIcnfYHxWZzk7L1yTVkRIzkFNyjNQp1oZTFeUXZMv4dQChq2 h1A2KfrYsodarh0GFEj1G8yKBZ0/AxIgAqO4VwdSeCVogkIFgZSY5LdBk3BVS8b1g8Lo +rAVtH8iJKGcRqNNC1DkH+k3OA8CUBAD9yN5hreOzosAuTUFqrtkQBwN4m83zfhrwNsR 0j7gvuWvLjkwB/DjE9ac55mT5VpvXkDv3GS5IAqM8uWcZSqGBbtdYE+hpI6nUWtaRyFW gAgkmEU7Y3TWKjkn+iY+PVjKX4YQDMklKOLpREqGFsdTE/3ca8tOn7w9grucZI3RODbc O0+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vrR3H5hGfnA2aTla5ccrl66sGlVMe3bSdnKTzLO2pcE=; b=VY5M4fD5SalA44mm9hkjCo0zxH/WtjgGJYS4ZJl1hbVSnVatWl0eRorunTgxrKjMLh 4+JGOJ5xQYQJOG3enIWyF5c3OELKFy3E3DCRbeViYbxrQf0W3mq76RRcuwBmLG8MpIR3 Azwj4hCNJ+Fr+FQglhfXzdWLKjIvHDb2n/SjYl42cXnEdiMfqRzcrZAFkAeq5Kh88Vbo K0DMywZTd0SV2RCAzboTRH1qyuaQjDK22RUDOOB/5+0IT6uivBspmk6aDT02KRHmejR/ PdNlzT4/raL3JljQsGTLv6qtWasSoqQhL6+N+P4B7Xx30wAcP2KCf/l/6Kep/TmdUIoS 7umw== X-Gm-Message-State: AMCzsaVqoMdSo9GVnnjFr18fI38W/d04UfJDt+fTqhqw0y/pYoz5qLFe y4reZVOr3vqLa/DVTJQM9InS9/OY X-Google-Smtp-Source: ABhQp+TTbLeWdwAODE7WZQL5ZqPQXpcRu55zvCVba1pxtEeHFIJNvBE8WrQLi6z3PHCIATpHVN9nHw== X-Received: by 10.46.91.66 with SMTP id p63mr11331778ljb.22.1509083780756; Thu, 26 Oct 2017 22:56:20 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:02 +0200 Message-Id: <20171027055612.2488-4-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v4 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 7a5c137..cf39e36 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -331,7 +331,10 @@ typedef enum { WRDI =3D 0x4, RDSR =3D 0x5, WREN =3D 0x6, + BRRD =3D 0x16, + BRWR =3D 0x17, JEDEC_READ =3D 0x9f, + BULK_ERASE_60 =3D 0x60, BULK_ERASE =3D 0xc7, READ_FSR =3D 0x70, RDCR =3D 0x15, @@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s) s->write_enable =3D false; } break; + case BRWR: case EXTEND_ADDR_WRITE: s->ear =3D s->data[0]; break; @@ -1041,6 +1045,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state =3D STATE_READING_DATA; break; =20 + case BULK_ERASE_60: case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); @@ -1058,12 +1063,14 @@ static void decode_new_cmd(Flash *s, uint32_t value) case EX_4BYTE_ADDR: s->four_bytes_address_mode =3D false; break; + case BRRD: case EXTEND_ADDR_READ: s->data[0] =3D s->ear; s->pos =3D 0; s->len =3D 1; s->state =3D STATE_READING_DATA; break; + case BRWR: case EXTEND_ADDR_WRITE: if (s->write_enable) { s->needed_bytes =3D 1; --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509083928557670.5461260113024; Thu, 26 Oct 2017 22:58:48 -0700 (PDT) Received: from localhost ([::1]:55856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xf3-0006rz-NJ for importer@patchew.org; Fri, 27 Oct 2017 01:58:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xd2-0005YJ-P8 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xd2-0007oN-1s for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:24 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:46272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xd1-0007mL-Qx for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:23 -0400 Received: by mail-lf0-x242.google.com with SMTP id g70so6144019lfl.3 for ; Thu, 26 Oct 2017 22:56:23 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v4 04/13] m25p80: Add support for n25q512a11 and n25q512a13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemi=C5=84ski Reviewed-by: Alistair Francis --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index cf39e36..054dc6f 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -240,6 +240,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, + { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084061841205.7685279884364; Thu, 26 Oct 2017 23:01:01 -0700 (PDT) Received: from localhost ([::1]:55866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xhQ-0000QW-2t for importer@patchew.org; Fri, 27 Oct 2017 02:00:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xd8-0005bs-Rr for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xd3-0007r1-G3 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:26 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:46272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xd3-0007oj-91 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:25 -0400 Received: by mail-lf0-x243.google.com with SMTP id g70so6144077lfl.3 for ; Thu, 26 Oct 2017 22:56:25 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency. Also move out a define and remove two dubbel includ= ed headers (while touching the code). Finally, add 4 byte address commands to = the FlashCMD enum. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 35 ----------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..559fa79 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,44 +114,11 @@ =20 /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 =20 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 =20 -typedef enum { - READ =3D 0x3, - FAST_READ =3D 0xb, - DOR =3D 0x3b, - QOR =3D 0x6b, - DIOR =3D 0xbb, - QIOR =3D 0xeb, - - PP =3D 0x2, - DPP =3D 0xa2, - QPP =3D 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; - static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) =20 +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ =3D 0x3, READ_4 =3D 0x13, + FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, + DOR =3D 0x3b, DOR_4 =3D 0x3c, + QOR =3D 0x6b, QOR_4 =3D 0x6c, + DIOR =3D 0xbb, DIOR_4 =3D 0xbc, + QIOR =3D 0xeb, QIOR_4 =3D 0xec, + + PP =3D 0x2, PP_4 =3D 0x12, + DPP =3D 0xa2, + QPP =3D 0x32, QPP_4 =3D 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; =20 @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; =20 +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" =20 --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084201749485.5375975495376; Thu, 26 Oct 2017 23:03:21 -0700 (PDT) Received: from localhost ([::1]:55875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xjf-0002Ep-Tu for importer@patchew.org; Fri, 27 Oct 2017 02:03:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdE-0005hW-Hj for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xd7-0007wu-68 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:32 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:54226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xd6-0007ro-VA for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:29 -0400 Received: by mail-lf0-x242.google.com with SMTP id l23so6114467lfk.10 for ; Thu, 26 Oct 2017 22:56:26 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fRqYF8CFDz/pK31LLU9qzJCPi/b3TKwG8qgezqp+k/0=; b=Fs7VQTe/xIN8Yl65slwZNspFs+47AYaJVcQjIRE6qCjK5ywB4v7XVQptqAhH5vV1ku znr3JwPR0dcdnZ+GwuTgKbOB0TZQCjiDb+muHCwonDw8uxKnjiJxTvaTL79FgPl9JvkL HPLaVuDWoc/uKBvy5VWAMo4Hc+lBQhY2QR54ZJKYuQkKwkg31iCqfYMAFb7Hr/ZoZOit beLJK6RF4k0FPnBVC1a9Rc7yHHIMnEypsyTSdO9DmZ7G3XCyiFcxAkDNJ4CXVOgtykKd CnBtyQXourpZ6NblS/LPWtamh+pqZg71RwAU4uP3EH0f9xwDoXW7CxliqG22Jj4+Oy0q tNuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fRqYF8CFDz/pK31LLU9qzJCPi/b3TKwG8qgezqp+k/0=; b=nJZDpCSiHn8ah4ZbJTc5LrVRbQdzRE3lzbgg5Q5pk131yP4iWsKc0HsIC0mt3sB0+o 8SUv0ZtCEThyqwDabHAQm7QHt7lRgvdO7P125dA54WblrfH6rryeboLX/D5Sl1LmSqeF Iqq0ZaViyHlqed1zV+oeKUiadk10NCNy/BdmGQ3ZMszVxVonELtNCp3f2ksX/0VlxCOt VPE+0q3eDB5Iuyjo6VmXyagkWVOeX+LDKpqUzFD8UphUu2bZ0Cvd2e52ysWXy7EcWQRA Eg4O7a01ZJK2fRcp9vymRhmqjaPtXyq0y1uTHivnvNQnK2Ow54wtgt+WSO+9DOd596Rw O3dg== X-Gm-Message-State: AMCzsaVzLyPQp39XpCw6xys6isufSwRxgfJdhLRvbjP7VXjoIiZl+8Ci NdbEvQ0rTpbM9UtanDUnENGEr79U X-Google-Smtp-Source: ABhQp+RRazrp/yK9XgXVYlSkhNs5vVeg0PdqnPnOojuhpQIiUoR2Ipnelf6csG4T77tZH3F7f9+huw== X-Received: by 10.25.229.135 with SMTP id i7mr9086695lfk.87.1509083785044; Thu, 26 Oct 2017 22:56:25 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:05 +0200 Message-Id: <20171027055612.2488-7-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v4 06/13] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update striping functionality to be big-endian bit order and output even bits into flash memory connected to the lower QSPI bus and odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 559fa79..7accf5d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -208,14 +208,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): * - * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir =3D=3D false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir =3D=3D true) ----- { 52hebGDA, }} */ =20 static inline void stripe8(uint8_t *x, int num, bool dir) @@ -223,15 +223,15 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] =3D {0, 0}; - int bit[2] =3D {0, 0}; + int bit[2] =3D {0, 7}; int d =3D dir; =20 for (idx[0] =3D 0; idx[0] < num; ++idx[0]) { - for (bit[0] =3D 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |=3D x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] =3D 7; bit[0] !=3D -1; bit[0] +=3D -1) { + r[idx[!d]] |=3D x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] =3D (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1] +=3D -1; } } } @@ -266,8 +266,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { + int bus =3D num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); } =20 --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084067950435.64236418663245; Thu, 26 Oct 2017 23:01:07 -0700 (PDT) Received: from localhost ([::1]:55867 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xhQ-0000R1-Uo for importer@patchew.org; Fri, 27 Oct 2017 02:00:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50775) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdE-0005hY-HZ for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xd8-0007ys-LB for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:32 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:55654) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xd8-0007tl-A2 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:30 -0400 Received: by mail-lf0-x243.google.com with SMTP id p184so6104214lfe.12 for ; Thu, 26 Oct 2017 22:56:27 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=aGKFgdbj0b38fmsMvtquJO23hYlCdnRWQQRKAxnJ3gy4GRFdGUoeboNCoUEz7OQFzK 4Hl4IQyUwtvV/Z23v59gASLBESfQSVjNqINcVPenDsQe3rcUKCSIIs8+ITWDnNnH3l1e XNSFO/l3lr221C/v7Xgi9WLqi1hbJdEIXKPM1ioGMqRQk+nLAH0MG1CLcUaXqLUD2e2/ vJlPuI1FjEXx+TYHlPUikxBdveA3zZ5Da01oBF6tnpuFNnQXDcKeTuxUgfWH8XTMonF8 /W+Qa+Li6yB5TxZBPpa9RhCbD9frdAC8vALKFPiZ9kegIxoYWlS8VqkkjSML5TiPPcu8 CL3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=X90FEShyrOnz0HumqOgfbD4Gucj5TSaNs5qfE3yWav2jeQTZfLOIZmwGEq9ksqqL6Y Hx2LKf+E7kY75Qki4qiHHQR7yMhRbD5Kuyr1Z2SEBl0dNlbaRtLFwjxnVThGdmFNUh9d ieaxd6bXHghgdv5GPbH5Q80zfXXbiQtFo5iYDi18LI0CxdRjotQIAvzJcN+ZLO1HwxiT /Xk6hNKRRZ8jGAB5E46Erjx54XQIyGMGunYVlnNS53z4/G34UNyzULY3cos1Kv+crSmV dbnlu2/XarUOy50PxWtH1FCTe9espT2RDcF3kX/2zS3TI5fbgDxnQIPCiw1cgb6iz2b8 K0rA== X-Gm-Message-State: AMCzsaUohbr9AK7nlvv6vZyAW01mT7bVYfjbryXOJ6rDVi8arNflhX4d EFrB8+knZu2RL4YTT+nvPA9kLBrW X-Google-Smtp-Source: ABhQp+TfBq5EHsjinx3o9dfMTar/FmE36bHWXzHapheAKeXjLMQL9ZG4+mDJTnvfL1XuxCu6UorOUQ== X-Received: by 10.25.115.196 with SMTP id h65mr8674447lfk.203.1509083786439; Thu, 26 Oct 2017 22:56:26 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:06 +0200 Message-Id: <20171027055612.2488-8-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 07/13] xilinx_spips: Add support for RX discard and RX drain X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 167 +++++++++++++++++++++++++++++++++++++-= ---- include/hw/ssi/xilinx_spips.h | 6 ++ 2 files changed, 155 insertions(+), 18 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7accf5d..8634810 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -30,6 +30,7 @@ #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" +#include "hw/register.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -100,6 +101,14 @@ #define LQSPI_CFG_DUMMY_SHIFT 8 #define LQSPI_CFG_INST_CODE 0xFF =20 +#define R_CMND (0xc0 / 4) + #define R_CMND_RXFIFO_DRAIN (1 << 19) + FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) +#define R_CMND_EXT_ADD (1 << 15) + FIELD(CMND, RX_DISCARD, 8, 7) + FIELD(CMND, DUMMY_CYCLES, 2, 6) +#define R_CMND_DMA_EN (1 << 1) +#define R_CMND_PUSH_WAIT (1 << 0) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -116,7 +125,8 @@ #define LQSPI_ADDRESS_BITS 24 =20 #define SNOOP_CHECKING 0xFF -#define SNOOP_NONE 0xFE +#define SNOOP_ADDR 0xF0 +#define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 =20 static inline int num_effective_busses(XilinxSPIPS *s) @@ -146,9 +156,14 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT_L(0, "selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); + if (s->cs_lines_state[cs_to_set]) { + s->cs_lines_state[cs_to_set] =3D false; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); + } } else { DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); + s->cs_lines_state[cs_to_set] =3D true; } } if (xilinx_spips_cs_is_set(s, i, field)) { @@ -157,6 +172,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *= s) } if (!found) { s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; DB_PRINT_L(1, "moving to snoop check state\n"); } } @@ -203,7 +222,11 @@ static void xilinx_spips_reset(DeviceState *d) /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] =3D 0x01090106; s->regs[R_LQSPI_CFG] =3D R_LQSPI_CFG_RESET; + s->link_state =3D 1; + s->link_state_next =3D 1; + s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; + s->cmd_dummies =3D 0; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -238,14 +261,69 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) +{ + if (!qs) { + /* The SPI device is not a QSPI device */ + return -1; + } + + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 5; + default: + return -1; + } +} + +static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) +{ + switch (cmd) { + case PP_4: + case QPP_4: + case READ_4: + case QIOR_4: + case FAST_READ_4: + case DOR_4: + case QOR_4: + case DIOR_4: + return 4; + default: + return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; + } +} + static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) { int debug_level =3D 0; + XilinxQSPIPS *q =3D (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), + TYPE_XILINX_QSP= IPS); =20 for (;;) { int i; uint8_t tx =3D 0; uint8_t tx_rx[num_effective_busses(s)]; + uint8_t dummy_cycles =3D 0; + uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { @@ -258,54 +336,102 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] =3D fifo8_pop(&s->tx_fifo); } stripe8(tx_rx, num_effective_busses(s), false); - } else { + } else if (s->snoop_state >=3D SNOOP_ADDR) { tx =3D fifo8_pop(&s->tx_fifo); for (i =3D 0; i < num_effective_busses(s); ++i) { tx_rx[i] =3D tx; } + } else { + /* Extract a dummy byte and generate dummy cycles according to= the + * link state */ + tx =3D fifo8_pop(&s->tx_fifo); + dummy_cycles =3D 8 / s->link_state; } =20 for (i =3D 0; i < num_effective_busses(s); ++i) { int bus =3D num_effective_busses(s) - 1 - i; - DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); - tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); - DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + if (dummy_cycles) { + int d; + for (d =3D 0; d < dummy_cycles; ++d) { + tx_rx[0] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx= [0]); + } + } else { + DB_PRINT_L(debug_level, "tx =3D %02x\n", tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); + DB_PRINT_L(debug_level, "rx =3D %02x\n", tx_rx[i]); + } } =20 - if (fifo8_is_full(&s->rx_fifo)) { + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); + /* Do nothing */ + } else if (s->rx_discard) { + DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); + s->rx_discard -=3D 8 / s->link_state; + } else if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_INTR_STATUS] |=3D IXR_RX_FIFO_OVERFLOW; DB_PRINT_L(0, "rx FIFO overflow"); } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { stripe8(tx_rx, num_effective_busses(s), true); for (i =3D 0; i < num_effective_busses(s); ++i) { fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); + DB_PRINT_L(debug_level, "pushing striped rx byte\n"); } } else { + DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); } =20 + if (s->link_state_next_when) { + s->link_state_next_when--; + if (!s->link_state_next_when) { + s->link_state =3D s->link_state_next; + } + } + DB_PRINT_L(debug_level, "initial snoop state: %x\n", (unsigned)s->snoop_state); switch (s->snoop_state) { case (SNOOP_CHECKING): - switch (tx) { /* new instruction code */ - case READ: /* 3 address bytes, no dummy bytes/cycles */ - case PP: + /* Store the count of dummy bytes in the txfifo */ + s->cmd_dummies =3D xilinx_spips_num_dummies(q, tx); + addr_length =3D get_addr_length(s, tx); + if (s->cmd_dummies < 0) { + s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D SNOOP_ADDR + addr_length - 1; + } + switch (tx) { case DPP: - case QPP: - s->snoop_state =3D 3; - break; - case FAST_READ: /* 3 address bytes, 1 dummy byte */ case DOR: + case DOR_4: + s->link_state_next =3D 2; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case QPP: + case QPP_4: case QOR: - case DIOR: /* FIXME: these vary between vendor - set to spansi= on */ - s->snoop_state =3D 4; + case QOR_4: + s->link_state_next =3D 4; + s->link_state_next_when =3D addr_length + s->cmd_dummies; + break; + case DIOR: + case DIOR_4: + s->link_state =3D 2; break; - case QIOR: /* 3 address bytes, 2 dummy bytes */ - s->snoop_state =3D 6; + case QIOR: + case QIOR_4: + s->link_state =3D 4; break; - default: + } + break; + case (SNOOP_ADDR): + /* Address has been transmitted, transmit dummy cycles now if + * needed */ + if (s->cmd_dummies < 0) { s->snoop_state =3D SNOOP_NONE; + } else { + s->snoop_state =3D s->cmd_dummies; } break; case (SNOOP_STRIPING): @@ -483,6 +609,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, uint64_t value, unsigned size) { XilinxQSPIPS *q =3D XILINX_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(opaque); =20 xilinx_spips_write(opaque, addr, value, size); addr >>=3D 2; @@ -490,6 +617,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, if (addr =3D=3D R_LQSPI_CFG) { xilinx_qspips_invalidate_mmio_ptr(q); } + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + fifo8_reset(&s->rx_fifo); + } } =20 static const MemoryRegionOps qspips_ops =3D { @@ -632,6 +762,7 @@ static void xilinx_spips_realize(DeviceState *dev, Erro= r **errp) } =20 s->cs_lines =3D g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state =3D g_new0(bool, s->num_cs * s->num_busses); for (i =3D 0, cs =3D s->cs_lines; i < s->num_busses; ++i, cs +=3D s->n= um_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7f9e2fc..bac90a5 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -61,13 +61,19 @@ struct XilinxSPIPS { uint8_t num_busses; =20 uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; =20 Fifo8 rx_fifo; Fifo8 tx_fifo; =20 uint8_t num_txrx_bytes; + uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; }; --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084211818226.1711817660805; Thu, 26 Oct 2017 23:03:31 -0700 (PDT) Received: from localhost ([::1]:55878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xji-0002Io-UU for importer@patchew.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=Ku+/ZqXaz31L00N0Zy1aMwK1BzK9oez4ZMvB+cOo9w8aufduqlx9szapcznmKEh+54 vHqUM3JownQChCXzRcaodThCf8c5bJwtrksanGHj9wfvKJexNY3+2He2dxuTy7xMgaGA yAOY2qIkvijq4BkeKlmEivBuOMK9xdLn+LfoppkIZ2f6yvgHWZKN9dIsJU+Cx1yUkEz6 OZY94l7T2eF1U6Psbp5H0jhctAdSR7MX6dePFkOlx3xjOZn50xD+tKyR9s5PNmb1Wn+/ BoytLepd773zP8Edh1gIykNq6ToDi+KpO7lPgEE4G8ooD+XwiGjxT73o6rmFlFD55dtE eNbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vpZRZGjt3HVlXZ0SmhKjjPGcUs+V6p4eFU34G6UVJcA=; b=G5ovPKUAge6kd9tZ3peiiheF3BfYFqPMRS6mnZMLufdrqO/0Kdy33/rWnxysyHjyzJ Lh6auw4+ci5rViMfO8u+wLXzhFNyXCF7Fh0D409LkPmGciliritHs0XpV+1FnAUqbyLh 1K/HdRAhUywMaT5sPnfW7bKX4MmjG0IMVyl2aVJDOP6aD3wEFhRAGMJVOZiaCutBZ6NT kyuyW6V8M1348NdW6Naj2IvlXMHkBZyyBv2nrhZkAmO4fb/7TPOVDi58H1+CAvTk92XS W0jgutDDgdUMJVXEuaBLISelaBhm/Rpx73UxFUkGsLRiT2amntnWWFEIS/lz96v9vgp8 yVqA== X-Gm-Message-State: AMCzsaUfcoKKI52tu0aweOn+HZz7quRPh3WXKmtmj5cRu/2xNMyBfzxS iK7tEBS3Y0eGt0iYNhzyx3hu3Ddb X-Google-Smtp-Source: ABhQp+RuVl8EyKSub3cPqtng2TMuZzbS15yDOyuu64EVYryHeZzmRPqLmOtQ3DieS9Zt3rbWjYnjuA== X-Received: by 10.25.19.73 with SMTP id j70mr8562195lfi.240.1509083787859; Thu, 26 Oct 2017 22:56:27 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:07 +0200 Message-Id: <20171027055612.2488-9-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v4 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 64 +++++++++++++++++++++++++++++------------------= ---- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8634810..e37d005 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -450,13 +450,28 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } =20 -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, boo= l be) { int i; + for (i =3D 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<=3D 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>=3D 8; + } + } +} =20 - for (i =3D 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - value[i] =3D fifo8_pop(&s->rx_fifo); +static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) +{ + int i; + + for (i =3D 0; i < max && !fifo8_is_empty(fifo); ++i) { + value[i] =3D fifo8_pop(fifo); } + return max - i; } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -466,6 +481,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, uint32_t mask =3D ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; =20 addr >>=3D 2; switch (addr) { @@ -496,9 +512,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret =3D s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_b= uf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall =3D rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes= ); + ret =3D s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<=3D 8 * shortfall; + } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -509,20 +529,6 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, =20 } =20 -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i =3D 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<=3D 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>=3D 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -563,16 +569,20 @@ static void xilinx_spips_write(void *opaque, hwaddr a= ddr, mask =3D 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); @@ -682,11 +692,11 @@ static void lqspi_load_cache(void *opaque, hwaddr add= r) =20 while (cache_entry < LQSPI_CACHE_SIZE) { for (i =3D 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i =3D 0; i < 64; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); + rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1= ); } } =20 --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084206757260.65102656775287; Thu, 26 Oct 2017 23:03:26 -0700 (PDT) Received: from localhost ([::1]:55876 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xjj-0002IF-Dc for importer@patchew.org; Fri, 27 Oct 2017 02:03:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdF-0005m3-CC for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xdB-00082O-6u for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:34 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:46273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xdB-0007xs-00 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:33 -0400 Received: by mail-lf0-x243.google.com with SMTP id g70so6144241lfl.3 for ; Thu, 26 Oct 2017 22:56:30 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 09/13] xilinx_spips: Add support for zero pumping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++---= ---- include/hw/ssi/xilinx_spips.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e37d005..3a98799 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ FIELD(CMND, DUMMY_CYCLES, 2, 6) #define R_CMND_DMA_EN (1 << 1) #define R_CMND_PUSH_WAIT (1 << 0) +#define R_TRANSFER_SIZE (0xc4 / 4) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) =20 @@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d) s->link_state_next_when =3D 0; s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; + s->man_start_com =3D false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t= value, int num, bool be) } } =20 +static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) +{ + if (!s->regs[R_TRANSFER_SIZE]) { + return; + } + if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT= ) { + return; + } + /* + * The zero pump must never fill tx fifo such that rx overflow is + * possible + */ + while (s->regs[R_TRANSFER_SIZE] && + s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { + /* endianess just doesn't matter when zero pumping */ + tx_data_bytes(&s->tx_fifo, 0, 4, false); + s->regs[R_TRANSFER_SIZE] &=3D ~0x03ull; + s->regs[R_TRANSFER_SIZE] -=3D 4; + } +} + +static void xilinx_spips_check_flush(XilinxSPIPS *s) +{ + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } + if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { + s->man_start_com =3D false; + } + xilinx_spips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, uint64_t value, unsigned size) { int mask =3D ~0; - int man_start_com =3D 0; XilinxSPIPS *s =3D opaque; =20 DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); @@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, switch (addr) { case R_CONFIG: mask =3D ~(R_CONFIG_RSVD | MAN_START_COM); - if (value & MAN_START_COM) { - man_start_com =3D 1; + if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN))= { + s->man_start_com =3D true; } break; case R_INTR_STATUS: @@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr ad= dr, s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: xilinx_spips_update_cs_lines(s); - if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || - (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_= EN)) { - xilinx_spips_flush_txfifo(s); - } + xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index bac90a5..ad2175a 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -76,6 +76,8 @@ struct XilinxSPIPS { uint32_t rx_discard; =20 uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; =20 typedef struct { --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084332384975.9739405450525; Thu, 26 Oct 2017 23:05:32 -0700 (PDT) Received: from localhost ([::1]:55886 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xln-0003yE-If for importer@patchew.org; Fri, 27 Oct 2017 02:05:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdF-0005m7-EG for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xdC-00083a-H9 for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:35 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:57267) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xdC-00080n-9H for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:34 -0400 Received: by mail-lf0-x242.google.com with SMTP id 90so6118015lfs.13 for ; Thu, 26 Oct 2017 22:56:31 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9xWCi1U1MzTiqRRKJPWrpHbnKQEwWZwqcARbHEmA394=; b=U5WP3KxDOXAS5Dqw0mMsLg/sbQ5EmMWVt22IbCryNrtZQRXw9l0Lrg5jfl5iGolKte DQ4IDSetPkV52yPb/d7F9CnNLFFGhjdZkfSpg7LYDnYgiL76cMqVRGn+b6yEa0dZkZv6 WF2rfNLzouyq/MWbJbB6WTmDlnm2lmt3k7rWHOUIWnJNb3ZeGHQEEmi9RMbyYQM2wG1p eddtQZsKBGUfFOd3Xt4VOXGq/cR4m6SMwom2G9bGiF6AE796gCrkYt7kkEFB32t1tQZq /HJJVl7oIXt5HlrE81/C1lmerFuZwwNo++Lu006jFq1PhDY2H5yKjjqqyt7+4WxDtnlX x4gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9xWCi1U1MzTiqRRKJPWrpHbnKQEwWZwqcARbHEmA394=; b=XY1cx+TE9QNmfLxLn9fSj+38pCqvIHZQCp1KsMY71+ofXqy0TsrHndZVVr3uqOMBPH EE6/bJBu7NQQFCZj5H/DG3/57EBBw+TUjer4rOrRFHI8AnS06eA7epDTvBM+T21AK4jI eSytERlZYMMGFeOPgFkymwPteC7GmjJ2sBMgZbpKQ5OKiYv7bMeaPlZfIxwXks1FY5g9 R3+x+2EJ3dYevrtfo1LbRc4UX85uCORQ8+pKVRjBHjh40Tn451KPpplLKemClJ5g4iTb 1EA7UyuhJ1+uRJ9yfEY+dWF2g9H3kv5GptOK+1RuqEFRL1re/jiw6nZHKEhv38whpXYa BGBg== X-Gm-Message-State: AMCzsaVa2Sak+IRhM7um3nXuh0lDHEyZCPtn43lLGeD31UTROPSNVaQZ 7LmOXYCSR1Y1903upUTXMRLgXdZJ X-Google-Smtp-Source: ABhQp+RKqvsRUXhzjtEMx+5FYef8JZ/GMVyPmYJtthT2j/gQPiMrYimk+oKjud7YXjevf6QRaBq85w== X-Received: by 10.46.67.14 with SMTP id q14mr10475077lja.73.1509083790509; Thu, 26 Oct 2017 22:56:30 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:09 +0200 Message-Id: <20171027055612.2488-11-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v4 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 3a98799..7f0f317 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE= ); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084346545882.4821032436761; Thu, 26 Oct 2017 23:05:46 -0700 (PDT) Received: from localhost ([::1]:55885 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xlm-0003xG-Ez for importer@patchew.org; Fri, 27 Oct 2017 02:05:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdF-0005m8-Kv for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xdD-00085c-Pn for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:36 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:44270) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xdD-00081m-JG for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:35 -0400 Received: by mail-lf0-x244.google.com with SMTP id 75so6150652lfx.1 for ; Thu, 26 Oct 2017 22:56:33 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=COSloL/ftBNnusipGbzRX1hiEpkahH+vGQYBhSwo2zx0Mz2tfgcyAuR3XIV7XNWxk8 05Jjtn6gjs3HN3krOK55QqI/O8grLQqJJ479EqdXh7yKqjEGXtfT9qs5aFKwqnDMw4XF EE0fxvMcbNR9dUHvxRbx7f+Df+HF84aJ8w0n7AQUL3ACkpT7g7S2YYX6KjbEVNneuQps wPQxzRGSbmIe0ky06RepUFA15CLdzcYzp2tA+IZscrw8mjiJqA8m6yPgw9gofIBSGnbu 5BpkhW2w0pdydTiVuQ3iR75J1Z2ZkiE/PkM9NuEe7bPbg5VmPXdvRPDOaZTe6KoML21N bDHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=hAsHSX48Lc8ft5g6uUqbtRlpwWyghaTAcen7ROlnTwmYxmazLBxCpY63K666f0yVQd pBtLC4W2kuuxwkodSQ78cWGB8VmB0rZJWYn+bEhUU5tpvnQ5hro+WsY1SJQGYX9IRKto V3T0/eQsS72HSL5c5ykgRMTwpX2ssHzrX+1tcuTburgBB64o4h1FHWGjjJTOXptk0DPi HXx3CNcZM78YwOfEGXIoZxJRnGUpZqHidxVRijB78wAdKkHckmH8+WwfrFAXgU4BS4sP 7xjDJBVjaZ9ncSD9haLI0rLXF5XDGVUoi1MQtHAUZS4X+6IOaol1hkKvy0P4R2n5deJi eWlA== X-Gm-Message-State: AMCzsaWQlZ5qIp+83XklbA9rW1h9liyxURUD4n2kraBBmJiwm8ynE0Fb Zid1bnCu6SnhC4Bt8kXx6bQP7h/k X-Google-Smtp-Source: ABhQp+Soo/ljCPn8+XIBbA++Tl+eg790UplPzO/x2WYWL6Ypj6HZkbOi+/CQlQSqYFh7O1UjqeogVQ== X-Received: by 10.46.74.10 with SMTP id x10mr10308910lja.91.1509083791842; Thu, 26 Oct 2017 22:56:31 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:10 +0200 Message-Id: <20171027055612.2488-12-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v4 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7f0f317..159a89d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; =20 if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |=3D IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state =3D=3D SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr = addr, ret =3D s->regs[addr] & IXR_ALL; s->regs[addr] =3D 0; DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask =3D IXR_ALL; --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084435972634.181468096758; Thu, 26 Oct 2017 23:07:15 -0700 (PDT) Received: from localhost ([::1]:55898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xnQ-0005SX-4R for importer@patchew.org; Fri, 27 Oct 2017 02:07:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdI-0005qM-JX for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xdE-00086I-NX for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:39 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:44271) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xdE-00083M-8h for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:36 -0400 Received: by mail-lf0-x241.google.com with SMTP id 75so6150717lfx.1 for ; Thu, 26 Oct 2017 22:56:34 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yPLNuSYCBeWhK6+pCBAfUvIwcpXLsH/rVeEIuK0zETE=; b=sREeOFUD3SZEUi0GpUJP6zYd3SwPPvZAAgNm8KFNUWTbvRhkovSEX2C8Re2E0JHuJ5 QXv+szmr/iF05B+uY1fp4YwuKWawByp8bJZufpbsDJiHkPVTr5WRZAxhHWtALcUZzop2 w4YfXHXba6BlIRY174cDbFmgqnFAKPmvvlk7PziBsAlKF+Kr0x3PEl4ESjPY1AdNmeao 8ZX00tG7s6ypxHLaLMn3OxeexIIrtpTMP3a74G66OzQpZGrt52wEsPCqiXqL9fLMnwxP C/STx99vALw0tN0LM0KoJWp37tz2Km3CSRFFoBJz40BrJsM7bQdcAiUKiPvUrdgBEi6X 3mOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yPLNuSYCBeWhK6+pCBAfUvIwcpXLsH/rVeEIuK0zETE=; b=r4AiPzfKvU4XhHgWmQgL6NU6ehNUTg7aFBpJcxo54bU5SXSgEZBXP92w51yu5gsFGB 6rayJxw+rWt4O9vZ6NPj3WJTHgspiyAfVKjD4F1PSn+YGU86VYWk96Y3oZ4WO6P1zl6h bRwB5zuPa00w4Qt0UGFJEV/4S6pz5tLbRy99FbXbqbYBuX7pRtT+MxqBEjlP0J97vjxy Q2GdLN1fbI7cZQPljTPUEu426AZLBVlST/wY74vJPpxxuwyjvq8stSVQG6ui1bBFNJ4S emQIkF9MGdtQ579xLj49rPk3cy+OL/n7MIOQwqMvVi6aj2CnBwqb+iCT6ewNrA82foTC I56g== X-Gm-Message-State: AMCzsaVv8aqZj6JuAxChBvV+cOdWrgTRn50M94yH9uFeOMhnu/XWXCtW 8CTVXaKcgfg2nIiMipzh2xHJroMW X-Google-Smtp-Source: ABhQp+Q0GEUPehxr0Fuha2864jObt4dZdRX7VvwIRiW4yTrbBnlWAirOW8PDUXRAjNO3qj2oGRdNGA== X-Received: by 10.46.48.6 with SMTP id w6mr1248583ljw.16.1509083793300; Thu, 26 Oct 2017 22:56:33 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:11 +0200 Message-Id: <20171027055612.2488-13-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v4 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias --- default-configs/arm-softmmu.mak | 1 + hw/ssi/xilinx_spips.c | 449 +++++++++++++++++++++++++++++++++++-= ---- include/hw/ssi/xilinx_spips.h | 29 ++- 3 files changed, 429 insertions(+), 50 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 5059d13..d09fd34 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,3 +130,4 @@ CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy CONFIG_MSF2=3Dy +CONFIG_XILINX_AXI=3Dy diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 159a89d..f8d2018 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" =20 #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,30 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) =20 #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -116,9 +134,54 @@ =20 #define R_MOD_ID (0xFC / 4) =20 +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) +#define R_GQSPI_GEN_FIFO (0x140 / 4) +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) +#define R_GQSPI_DATA_STS (0x15c / 4) +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) =20 #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -137,42 +200,54 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } =20 -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) +static void xilinx_spips_update_cs_lines_legacy(XilinxSPIPS *s, int *field) { - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); + *field =3D ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) =3D=3D 2) { + /* Single bit chip-select for qspi */ + *field &=3D 0x1; + *field |=3D *field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + *field &=3D 0x1; + /* change from CS0 to CS1 */ + *field <<=3D 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + *field =3D 0; + } } =20 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) { - int i, j; - bool found =3D false; - int field =3D s->regs[R_CONFIG] >> CS_SHIFT; + int i; + int field =3D 0; =20 + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + xilinx_spips_update_cs_lines_legacy(s, &field); + } else if (s->regs[R_GQSPI_GF_SNAPSHOT]) { + field =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT= ); + } else { + /* Do nothing */ + return; + } for (i =3D 0; i < s->num_cs; i++) { - for (j =3D 0; j < num_effective_busses(s); j++) { - int upage =3D !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set =3D (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - if (s->cs_lines_state[cs_to_set]) { - s->cs_lines_state[cs_to_set] =3D false; - s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_D= ISCARD); - } - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - s->cs_lines_state[cs_to_set] =3D true; - } - } - if (xilinx_spips_cs_is_set(s, i, field)) { - found =3D true; + bool old_state =3D s->cs_lines_state[i]; + bool new_state =3D field & (1 << i); + + if (old_state !=3D new_state) { + s->cs_lines_state[i] =3D new_state; + s->rx_discard =3D ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(0, "%sselecting slave %d\n", new_state ? "" : "de",= i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; s->link_state =3D 1; @@ -184,22 +259,46 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS = *s) =20 static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + int new_irqline; + uint32_t qspi_int; + uint32_t gqspi_int; + + s->regs[R_GQSPI_ISR] &=3D ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |=3D + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >=3D s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &=3D ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |=3D + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL := 0); + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + s->regs[R_INTR_STATUS] |=3D fifo8_is_empty(&s->tx_fifo) ? + IXR_TX_FIFO_EMPTY : 0; + } } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &=3D (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERF= LOW | - IXR_TX_FIFO_MODE_FAIL); - /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |=3D - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >=3D s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY := 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); + /* QSPI/SPI Interrupt Trigger Status */ + qspi_int =3D s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS]; + /* GQSPI Interrupt Trigger Status */ + gqspi_int =3D (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_I= XR_MASK; /* drive external interrupt pin */ - int new_irqline =3D !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & - IXR_ALL); + new_irqline =3D !!((qspi_int | gqspi_int) & IXR_ALL); if (new_irqline !=3D s->irqline) { + DB_PRINT_L(0, "IRQ state: %x -> %x\n", s->irqline, new_irqline); s->irqline =3D new_irqline; qemu_set_irq(s->irq, s->irqline); } @@ -216,11 +315,18 @@ static void xilinx_spips_reset(DeviceState *d) =20 fifo8_reset(&s->rx_fifo); fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); /* non zero resets */ s->regs[R_CONFIG] |=3D MODEFAIL_GEN_EN; s->regs[R_SLAVE_IDLE_COUNT] =3D 0xFF; s->regs[R_TX_THRES] =3D 1; s->regs[R_RX_THRES] =3D 1; + s->regs[R_GQSPI_TX_THRESH] =3D 1; + s->regs[R_GQSPI_RX_THRESH] =3D 1; + s->regs[R_GQSPI_GFIFO_THRESH] =3D 1; + s->regs[R_GQSPI_IMR] =3D GQSPI_IXR_MASK; /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] =3D 0x01090106; s->regs[R_LQSPI_CFG] =3D R_LQSPI_CFG_RESET; @@ -230,6 +336,7 @@ static void xilinx_spips_reset(DeviceState *d) s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; s->man_start_com =3D false; + s->man_start_com_g =3D false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -264,6 +371,108 @@ static inline void stripe8(uint8_t *x, int num, bool = dir) memcpy(x, r, sizeof(uint8_t) * num); } =20 +static void xilinx_spips_flush_fifo_g(XilinxSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2] =3D { 0 }; + int num_stripes =3D 1; + uint8_t busses; + int i; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] =3D fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSH= OT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing= "); + continue; + } + xilinx_spips_update_cs_lines(s); + + imm =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE= _DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)= || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))= { + s->regs[R_GQSPI_DATA_STS] =3D 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] =3D 0; + } + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONE= NT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer to= o" + " long - 2 ^ %" PRId8 " requested\n", im= m); + } + s->regs[R_GQSPI_DATA_STS] =3D 1ul << imm; + } else { + s->regs[R_GQSPI_DATA_STS] =3D imm; + } + } + /* Zero length transfer check */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && + (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { + num_stripes =3D 2; + } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] =3D ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT))= { + for (i =3D 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] =3D fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes =3D=3D 1) { + /* mirror */ + tx_rx[1] =3D tx_rx[0]; + } + busses =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_S= ELECT); + for (i =3D 0; i < 2; ++i) { + DB_PRINT_L(1, "bus %d tx =3D %02x\n", i, tx_rx[i]); + tx_rx[i] =3D ssi_transfer(s->spi[i], tx_rx[i]); + DB_PRINT_L(1, "bus %d rx =3D %02x\n", i, tx_rx[i]); + } + if (s->regs[R_GQSPI_DATA_STS] > 1 && + busses =3D=3D 0x3 && num_stripes =3D=3D 2) { + s->regs[R_GQSPI_DATA_STS] -=3D 2; + } else if (s->regs[R_GQSPI_DATA_STS] > 0) { + s->regs[R_GQSPI_DATA_STS]--; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i =3D 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte =3D %02x\n", i, tx_rx[= i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -487,15 +696,27 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS = *s) =20 static void xilinx_spips_check_flush(XilinxSPIPS *s) { - if (s->man_start_com || - (!fifo8_is_empty(&s->tx_fifo) && - !(s->regs[R_CONFIG] & MAN_START_EN))) { - xilinx_spips_check_zero_pump(s); - xilinx_spips_flush_txfifo(s); + bool gqspi_has_work =3D s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)))= { + xilinx_spips_flush_fifo_g(s); + } + } else { + if (s->man_start_com || (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } } if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { s->man_start_com =3D false; } + if (!gqspi_has_work) { + s->man_start_com_g =3D false; + } xilinx_spips_update_ixr(s); } =20 @@ -509,6 +730,53 @@ static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *= value, int max) return max - i; } =20 +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max =3D=3D 0 || max > fifo->num) { + abort(); + } + *num =3D MIN(fifo->capacity - fifo->head, max); + ret =3D &fifo->data[fifo->head]; + fifo->head +=3D *num; + fifo->head %=3D fifo->capacity; + fifo->num -=3D *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s =3D XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, MODE_EN) =3D=3D 2)) { + return; + } + recv_fifo =3D &s->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo =3D &s->rx_fifo; + } + while (recv_fifo->num >=3D 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd =3D pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret =3D stream_push(rq->dma, rq->dma_buf, 4); + assert(ret =3D=3D 4); + xilinx_spips_check_flush(s); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -556,6 +824,23 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr= addr, ret <<=3D 8 * shortfall; } DB_PRINT_L(0, "addr=3D" TARGET_FMT_plx " =3D %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); + xilinx_spips_update_ixr(s); + return ret; + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, "Read from empty GQSPI RX FIFO\= n"); + return 0; + } + memset(rx_buf, 0, sizeof(rx_buf)); + shortfall =3D rx_data_bytes(&s->rx_fifo_g, rx_buf, s->num_txrx_byt= es); + ret =3D ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { + ret <<=3D 8 * shortfall; + } + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -619,6 +904,49 @@ static void xilinx_spips_write(void *opaque, hwaddr ad= dr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + case R_GQSPI_CNFG: + mask =3D ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { + s->man_start_com_g =3D true; + } + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + goto no_reg_update; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + goto no_reg_update; + case R_GQSPI_FIFO_CTRL: + mask =3D 0; + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |=3D value; + goto no_reg_update; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &=3D ~value; + goto no_reg_update; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &=3D ~value; + goto no_reg_update; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + mask =3D 0; + break; } s->regs[addr] =3D (s->regs[addr] & ~mask) | (value & mask); no_reg_update: @@ -662,6 +990,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { fifo8_reset(&s->rx_fifo); } + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + xlnx_zynqmp_qspips_notify(s); + } } =20 static const MemoryRegionOps qspips_ops =3D { @@ -825,6 +1156,9 @@ static void xilinx_spips_realize(DeviceState *dev, Err= or **errp) =20 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); } =20 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) @@ -856,6 +1190,17 @@ static void xilinx_qspips_realize(DeviceState *dev, E= rror **errp) } } =20 +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq =3D XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAV= E, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -936,10 +1281,18 @@ static const TypeInfo xilinx_qspips_info =3D { .class_init =3D xilinx_qspips_class_init, }; =20 +static const TypeInfo xlnx_zynqmp_qspips_info =3D { + .name =3D TYPE_XLNX_ZYNQMP_QSPIPS, + .parent =3D TYPE_XILINX_QSPIPS, + .instance_size =3D sizeof(XlnxZynqMPQSPIPS), + .instance_init =3D xlnx_zynqmp_qspips_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } =20 type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index ad2175a..35f6a6f 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,12 @@ #define XILINX_SPIPS_H =20 #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" =20 typedef struct XilinxSPIPS XilinxSPIPS; =20 -#define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_SPIPS_R_MAX 0x200 =20 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -71,6 +72,18 @@ struct XilinxSPIPS { =20 Fifo8 rx_fifo; Fifo8 tx_fifo; + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * at the end of each generic command, misaligned extra bytes are disc= ard + * or padded to tx and rx respectively to round it out (and avoid need= for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; =20 uint8_t num_txrx_bytes; uint32_t rx_discard; @@ -78,6 +91,7 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; =20 bool man_start_com; + bool man_start_com_g; }; =20 typedef struct { @@ -89,6 +103,13 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; =20 +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; =20 @@ -100,6 +121,7 @@ typedef struct XilinxSPIPSClass { =20 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" =20 #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -111,4 +133,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) =20 +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ --=20 2.9.3 From nobody Sat Nov 1 22:17:30 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509084383263686.2749080894513; Thu, 26 Oct 2017 23:06:23 -0700 (PDT) Received: from localhost ([::1]:55892 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xmZ-0004iP-De for importer@patchew.org; Fri, 27 Oct 2017 02:06:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e7xdG-0005mB-Oa for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e7xdE-000860-Jt for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:37 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:46274) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e7xdE-00084w-8M for qemu-devel@nongnu.org; Fri, 27 Oct 2017 01:56:36 -0400 Received: by mail-lf0-x243.google.com with SMTP id g70so6144391lfl.3 for ; Thu, 26 Oct 2017 22:56:36 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id r90sm1768334ljb.64.2017.10.26.22.56.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 22:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FxqozAvdH79IZ44nRaWYysAIWN35c/c3WaebQGuxRd4=; b=Bz/UILSXUZAiFILS9ONQW2qs7QJDu/q/Se7erRGZKwPndx06XDlJi7LFWrlwlYPmS7 Ph0pgphK5WrCuha2mF/ssBcjf4ZBhcwLiRK5Bfbs62F/is62ox30KFyy4N1aHOppEAmD 1HBDjUBJUAfYMo1bUCAZHWOPpn+bXRkNQ9B5dPXNGBiBtGTx2Pk5Jz62bdG0XDgGOx9r lTgL1qj603U3NuPchunLAadMgnIEOOjmgTxommgmasCCyPHPjPchSvybf/O5gAG3TW4m LssDAqaY38Dh1CbrhMdeMeV+3vCBMShmPdn7qwBINggjJeaV2hh0T1/8xYGSUEe5tZT8 R6og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FxqozAvdH79IZ44nRaWYysAIWN35c/c3WaebQGuxRd4=; b=A22SrxRf2H9tefuHDHg9keS8G7vdn5QL/p0kMmN0zZqltTakJp6o/33Y7ISLAOg/cf qusXWBV1pxvunFiaAe/0dMBSbPiyg3Mb3oTY6dDfr6teaCsD5YMDLEAW2ZgLk6or5u7S 2lQqbBZE7P1xCkqwKqxfpUiCJ/vV8gHL2fZHcl75nawQVKQpzkw42xjq1bvCxki03EAK WdcGu1s+Nt1/ghSwoaCQ1L5meQK6XXpTy0zXN/v5F0JiowvzLW+fyBl97RgOxgWFU6AQ 88XTxWPD9V5qNkDpXiegV67DtNQjQ0z7PbW3XV/7VVF9F79NfrK05D2VdlLV2gypKVbK DkFg== X-Gm-Message-State: AMCzsaX+mnCSsZhX3uLu+bVlaFKz2nlQY6jsExho9RTcIr7zWyumWiSZ CUc8i399CEseg6Aty9ox3PzJbw== X-Google-Smtp-Source: ABhQp+TH+QqmCtX3917oJdmsMQzAxBfPTh37WwhMJ+sGrMZQNAHaBRi5CnvUNOje3xvZqELrBFtFiw== X-Received: by 10.46.20.79 with SMTP id 15mr10093496lju.125.1509083794616; Thu, 26 Oct 2017 22:56:34 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Fri, 27 Oct 2017 07:56:12 +0200 Message-Id: <20171027055612.2488-14-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171027055612.2488-1-frasse.iglesias@gmail.com> References: <20171027055612.2488-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 24 ++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 52 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..7d61972 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -150,6 +150,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineSta= te *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo =3D drive_get_next(IF_MTD); + int bus =3D i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name =3D g_strdup_printf("qspi%d", bus); + + spi_bus =3D (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name= ); + g_free(bus_name); + + flash_dev =3D ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(di= nfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ =20 xlnx_zcu102_binfo.ram_size =3D ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..f7c8b4b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 =20 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 =20 @@ -169,6 +173,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } =20 + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); =20 @@ -405,6 +412,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) g_free(bus_name); } =20 + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + for (i =3D 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + /* Alias controller SPI bus to the SoC itself */ + bus_name =3D g_strdup_printf("qspi%d", i); + target_bus =3D g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 =20 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; =20 --=20 2.9.3