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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 1/4] target/i386: Decode AMD XOP prefix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, ehabkost@redhat.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 7df9233ded..db88cc4764 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4536,8 +4536,9 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) #endif case 0xc5: /* 2-byte VEX */ case 0xc4: /* 3-byte VEX */ + case 0x8f: /* 3-byte XOP */ /* VEX prefixes cannot be used except in 32-bit mode. - Otherwise the instruction is LES or LDS. */ + Otherwise the instruction is LES, LDS, or POP. */ if (s->code32 && !s->vm86) { static const int pp_prefix[4] =3D { 0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ @@ -4546,7 +4547,13 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) =20 if (!CODE64(s) && (vex2 & 0xc0) !=3D 0xc0) { /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b, - otherwise the instruction is LES or LDS. */ + otherwise the instruction is LES, LDS, or POP. */ + break; + } + if (b =3D=3D 0x8f && (vex2 & 0x1f) < 8) { + /* If the value of the XOP.map_select field is less than 8, + the first two bytes of the three-byte XOP are interpret= ed + as a form of the POP instruction. */ break; } s->pc++; @@ -4572,18 +4579,25 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) #endif vex3 =3D x86_ldub_code(env, s); rex_w =3D (vex3 >> 7) & 1; - switch (vex2 & 0x1f) { - case 0x01: /* Implied 0f leading opcode bytes. */ - b =3D x86_ldub_code(env, s) | 0x100; - break; - case 0x02: /* Implied 0f 38 leading opcode bytes. */ - b =3D 0x138; - break; - case 0x03: /* Implied 0f 3a leading opcode bytes. */ - b =3D 0x13a; - break; - default: /* Reserved for future use. */ - goto unknown_op; + if (b =3D=3D 0xc4) { + switch (vex2 & 0x1f) { + case 0x01: /* Implied 0f leading opcode bytes. */ + b =3D x86_ldub_code(env, s) | 0x100; + break; + case 0x02: /* Implied 0f 38 leading opcode bytes. */ + b =3D 0x138; + break; + case 0x03: /* Implied 0f 3a leading opcode bytes. */ + b =3D 0x13a; + break; + default: /* Reserved for future use. */ + goto unknown_op; + } + } else { + /* Unlike VEX, XOP.map_select does not overlap the + base instruction set. Prepend the map_select to + the next opcode byte. */ + b =3D x86_ldub_code(env, s) + (vex2 & 0x1f) * 0x100; } } s->vex_v =3D (~vex3 >> 3) & 0xf; @@ -8307,6 +8321,10 @@ static target_ulong disas_insn(DisasContext *s, CPUS= tate *cpu) case 0x1d0 ... 0x1fe: gen_sse(env, s, b, pc_start, rex_r); break; + + case 0x800 ... 0x8ff: /* XOP opcode map 8 */ + case 0x900 ... 0x9ff: /* XOP opcode map 9 */ + case 0xa00 ... 0xaff: /* XOP opcode map 10 */ default: goto unknown_op; } --=20 2.13.6