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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v2 16/27] i.MX: Add code to emulate GPCv2 IP block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrey Smirnov , Jason Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daud=C3=A9 Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/intc/Makefile.objs | 2 +- hw/intc/imx_gpcv2.c | 125 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/intc/imx_gpcv2.h | 22 ++++++++ 3 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 hw/intc/imx_gpcv2.c create mode 100644 include/hw/intc/imx_gpcv2.h diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 78426a7daf..db234901aa 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -4,7 +4,7 @@ common-obj-$(CONFIG_PL190) +=3D pl190.o common-obj-$(CONFIG_PUV3) +=3D puv3_intc.o common-obj-$(CONFIG_XILINX) +=3D xilinx_intc.o common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_pic.o -common-obj-$(CONFIG_IMX) +=3D imx_avic.o +common-obj-$(CONFIG_IMX) +=3D imx_avic.o imx_gpcv2.o common-obj-$(CONFIG_LM32) +=3D lm32_pic.o common-obj-$(CONFIG_REALVIEW) +=3D realview_gic.o common-obj-$(CONFIG_SLAVIO) +=3D slavio_intctl.o diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c new file mode 100644 index 0000000000..496ed31b78 --- /dev/null +++ b/hw/intc/imx_gpcv2.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 GPCv2 block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/intc/imx_gpcv2.h" +#include "qemu/log.h" + +#define GPC_PU_PGC_SW_PUP_REQ 0x0f8 +#define GPC_PU_PGC_SW_PDN_REQ 0x104 + +#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4) +#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3) +#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2) +#define PCIE_PHY_SW_Pxx_REQ BIT(1) +#define MIPI_PHY_SW_Pxx_REQ BIT(0) + + +static void imx_gpcv2_reset(DeviceState *dev) +{ + IMXGPCv2State *s =3D IMX_GPCV2(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static uint64_t imx_gpcv2_read(void *opaque, hwaddr offset, + unsigned size) +{ + IMXGPCv2State *s =3D opaque; + + return s->regs[offset / sizeof(uint32_t)]; +} + +static void imx_gpcv2_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + IMXGPCv2State *s =3D opaque; + const size_t idx =3D offset / sizeof(uint32_t); + + s->regs[idx] =3D value; + + /* + * Real HW will clear those bits once as a way to indicate that + * power up request is complete + */ + if (offset =3D=3D GPC_PU_PGC_SW_PUP_REQ || + offset =3D=3D GPC_PU_PGC_SW_PDN_REQ) { + s->regs[idx] &=3D ~(USB_HSIC_PHY_SW_Pxx_REQ | + USB_OTG2_PHY_SW_Pxx_REQ | + USB_OTG1_PHY_SW_Pxx_REQ | + PCIE_PHY_SW_Pxx_REQ | + MIPI_PHY_SW_Pxx_REQ); + } +} + +static const struct MemoryRegionOps imx_gpcv2_ops =3D { + .read =3D imx_gpcv2_read, + .write =3D imx_gpcv2_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx_gpcv2_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMXGPCv2State *s =3D IMX_GPCV2(obj); + + memory_region_init_io(&s->iomem, + obj, + &imx_gpcv2_ops, + s, + TYPE_IMX_GPCV2 ".iomem", + sizeof(s->regs)); + sysbus_init_mmio(sd, &s->iomem); +} + +static const VMStateDescription vmstate_imx_gpcv2 =3D { + .name =3D TYPE_IMX_GPCV2, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IMXGPCv2State, GPC_NUM), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx_gpcv2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D imx_gpcv2_reset; + dc->vmsd =3D &vmstate_imx_gpcv2; + dc->desc =3D "i.MX GPCv2 Module"; +} + +static const TypeInfo imx_gpcv2_info =3D { + .name =3D TYPE_IMX_GPCV2, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMXGPCv2State), + .instance_init =3D imx_gpcv2_init, + .class_init =3D imx_gpcv2_class_init, +}; + +static void imx_gpcv2_register_type(void) +{ + type_register_static(&imx_gpcv2_info); +} +type_init(imx_gpcv2_register_type) diff --git a/include/hw/intc/imx_gpcv2.h b/include/hw/intc/imx_gpcv2.h new file mode 100644 index 0000000000..ed978b24bb --- /dev/null +++ b/include/hw/intc/imx_gpcv2.h @@ -0,0 +1,22 @@ +#ifndef IMX_GPCV2_H +#define IMX_GPCV2_H + +#include "hw/sysbus.h" + +enum IMXGPCv2Registers { + GPC_NUM =3D 0xE00 / sizeof(uint32_t), +}; + +typedef struct IMXGPCv2State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + uint32_t regs[GPC_NUM]; +} IMXGPCv2State; + +#define TYPE_IMX_GPCV2 "imx-gpcv2" +#define IMX_GPCV2(obj) OBJECT_CHECK(IMXGPCv2State, (obj), TYPE_IMX_GPCV2) + +#endif /* IMX_GPCV2_H */ --=20 2.13.5