From nobody Mon Feb 9 14:02:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508635317280262.2803175605161; Sat, 21 Oct 2017 18:21:57 -0700 (PDT) Received: from localhost ([::1]:59732 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64xb-0001we-ED for importer@patchew.org; Sat, 21 Oct 2017 21:21:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61j0-0000OM-3a for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61iy-0002MI-Mf for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:34 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:51664) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61iy-0002I2-F8 for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: by mail-lf0-x244.google.com with SMTP id r129so16443549lff.8 for ; Sat, 21 Oct 2017 14:54:32 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eTuc2E1/iSb4OMamGe+sju0ul3InQlHCb5VgukXOOeM=; b=AlNuB3Tvsp6lPgreKAU3QSESfZKBzM1w7PvQbi3seGK6ri6vDXzWEhe6/E6dxYxn48 MN9tOUa0rU90L4QK0FZL0SV3PPVANEZTzKN/vVqdYNfEQI1UMUUHJaw5Igq+st/1Nf08 934r/ISyvNvwRyfAgtwIURe5SBBcjS3R9X9HFDKdFfCf33KyHbeup2Sf45JgFQs6qF3w ou7mkNUhD/KI0jynFUWc4WCQvOHzvWWwl2hDlwL0xaY5OUPc94Mkis7H/NXU+IDb7ji5 +a5Af+F6BJ690LOJRVsdvFt89r6rJ/ESmZYPPPOrp9MSj4tNuxF/LHYKScD1QKrCxxMx JzyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eTuc2E1/iSb4OMamGe+sju0ul3InQlHCb5VgukXOOeM=; b=OabgmxR2yBBSETKnrlhsUV9AqM4bVccSZ0mb8n+qJoliIcREHY1P4MqNT0+cOK1HuC F0J++jLDudzWCcWmWkBBN07gJsR866WKmVjnbAokHe6lV6wQpWWVtmhlQNHkuPLM8WIu dhaBXpqwOUfpZaDmJ7qyYSYx9Jd72cp6mrJ7a1anyTePSOmxTaa90WNqy9SPKAjTF9di z9RWwNLul3Sfd6fp/+lI0x3h5/INtiYG0nsVHOb9IZSLaDsKIg1649aFEtnJTulDZ21Q 6zXXl/bIEyNsYkJdmrRtJ+DbMxViEFpNKwm/HpBa0gN3a3+c127WQnNYTstfRwULywSF PWQQ== X-Gm-Message-State: AMCzsaVdArMm586bhzkuLsQy1CwGcQ2zzYkI6RLGmbvSOUbl6T9hXLE6 rWJyKIYGciafLuqdLQNqcm8De4bu X-Google-Smtp-Source: ABhQp+TN61lUW7lLsIdOllakMnSsfV73wsmTLmAc7u1Lt9aV8Ps0N2HfuzJYgEu+xwRgOYoqmd56Mg== X-Received: by 10.46.69.6 with SMTP id s6mr3817123lja.76.1508622870617; Sat, 21 Oct 2017 14:54:30 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:13 +0200 Message-Id: <20171021215420.19787-6-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 05/12] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency. Also move out a define and remove two dubbel includ= ed headers (while touching the code). Finally, add 4 byte address commands to = the FlashCMD enum. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 34 ---------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..93b9e43 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,43 +114,11 @@ =20 /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 =20 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 =20 -typedef enum { - READ =3D 0x3, - FAST_READ =3D 0xb, - DOR =3D 0x3b, - QOR =3D 0x6b, - DIOR =3D 0xbb, - QIOR =3D 0xeb, - - PP =3D 0x2, - DPP =3D 0xa2, - QPP =3D 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; =20 static inline int num_effective_busses(XilinxSPIPS *s) { diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) =20 +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ =3D 0x3, READ_4 =3D 0x13, + FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, + DOR =3D 0x3b, DOR_4 =3D 0x3c, + QOR =3D 0x6b, QOR_4 =3D 0x6c, + DIOR =3D 0xbb, DIOR_4 =3D 0xbc, + QIOR =3D 0xeb, QIOR_4 =3D 0xec, + + PP =3D 0x2, PP_4 =3D 0x12, + DPP =3D 0xa2, + QPP =3D 0x32, QPP_4 =3D 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; =20 @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; =20 +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" =20 --=20 2.9.3