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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id j204sm577830itj.16.2017.10.20.07.39.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Oct 2017 07:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=P/1G6CFx3jvlVIYjUJEPxb96MqN53YmWr23k5gIz+nY=; b=hTMVMmMiVz/Jphf6HkzYseS8Zo53mAMy4DX78sqUi8KA9hK82MOJDGUVm8oJygTERs 9FF4UHnz+Og67x7M5PR2Bw3RGbCiWJJ/FZYD7qO8w2IRMO31glvXwMc+XVdAQ5ywGHa8 vkUWEYqAVNZLt9hzRMg5Am6D/7IGtjIrmY6x7zFWp5dMBUbYmhEfwMurYFd6i17BZt0m lEhYVhtUM0F1mxUZpQ7rlTqTcOBpQSSfs1bSObWlE64DNxdf4JNMyvxmB5oZiGEHx7QZ qi35uINJ5a/sCM/G+1teOb9sflTqZE3igq4YG5p1GHbA3yqcLSpY9+dqT5/4HMaM4Z37 iTaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=P/1G6CFx3jvlVIYjUJEPxb96MqN53YmWr23k5gIz+nY=; b=Ei3/I4oElpXcx1qpW9dyRZ8/26OmFmpDjdd4TnRgo1ez9AUviL7z/V7fRxVvjdVXhU moKT/G0ek2nU8bkJSrhxsr7cmxkbMd+2Tex+Jq89LpX2tdGlCbeip0dMgJPt08BZoO5h ch4kVe/vGLMbRJAfL0kqVznQQPtc9cTSxlN3mZyRtgFzF9reD1PQcmiVzUid6JCYj0EX BZT2gbJ98gWIXqnFxGwVc4oxk1WQi9RIULSFjjCuq9mA0w0D/DYp03AtIagTkCqbTON/ 0LfTqVJTv/O6hz9bRm4avNhRY1b/Jm1ZoEGILRv9Akk/DN+eROZSIv5bWQWm4pPhE7yf GyQw== X-Gm-Message-State: AMCzsaWa5Ie92HwgKxrLY9CMLKUQXNjHC8LBtKkT99clf03O+y4V1taU LTBKvaKd5stKio6RG+Ab0nk= X-Google-Smtp-Source: ABhQp+Q30vcFJAumCsZ8j2YWJp2pGVP7ECOYSK9Mmd6g3XtrRDNWidtHXLmKedDwKWHCz7iVpd7+EQ== X-Received: by 10.36.79.22 with SMTP id c22mr3052396itb.102.1508510371061; Fri, 20 Oct 2017 07:39:31 -0700 (PDT) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Fri, 20 Oct 2017 09:38:52 -0500 Message-Id: <20171020143852.2443-1-mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH] e500: ppce500_init_mpic() return device instead of IRQ array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Actual number of interrupt pins isn't known in ppce500_init_mpic() so a hardcoded number was used, which causes a crash with older openpic. Instead, return the DeviceState* and change ppce500_init() to call qdev_get_gpio_in() to get only the irq pins which are needed. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b8d786c479..33adc809ba 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -729,15 +729,13 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Para= ms *params, return dev; } =20 -static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *p= arams, - MemoryRegion *ccsr, qemu_irq **irqs) +static DeviceState *ppce500_init_mpic(MachineState *machine, + PPCE500Params *params, + MemoryRegion *ccsr, + qemu_irq **irqs) { - qemu_irq *mpic; DeviceState *dev =3D NULL; SysBusDevice *s; - int i; - - mpic =3D g_new0(qemu_irq, 256); =20 if (kvm_enabled()) { Error *err =3D NULL; @@ -756,15 +754,11 @@ static qemu_irq *ppce500_init_mpic(MachineState *mach= ine, PPCE500Params *params, dev =3D ppce500_init_mpic_qemu(params, irqs); } =20 - for (i =3D 0; i < 256; i++) { - mpic[i] =3D qdev_get_gpio_in(dev, i); - } - s =3D SYS_BUS_DEVICE(dev); memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, s->mmio[0].memory); =20 - return mpic; + return dev; } =20 static void ppce500_power_off(void *opaque, int line, int on) @@ -796,8 +790,8 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and * 4 respectively */ unsigned int pci_irq_nrs[PCI_NUM_PINS] =3D {1, 2, 3, 4}; - qemu_irq **irqs, *mpic; - DeviceState *dev; + qemu_irq **irqs; + DeviceState *dev, *mpicdev; CPUPPCState *firstenv =3D NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; @@ -866,18 +860,18 @@ void ppce500_init(MachineState *machine, PPCE500Param= s *params) memory_region_add_subregion(address_space_mem, params->ccsrbar_base, ccsr_addr_space); =20 - mpic =3D ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); + mpicdev =3D ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); =20 /* Serial */ if (serial_hds[0]) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, - 0, mpic[42], 399193, + 0, qdev_get_gpio_in(mpicdev, 42), 399193, serial_hds[0], DEVICE_BIG_ENDIAN); } =20 if (serial_hds[1]) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, - 0, mpic[42], 399193, + 0, qdev_get_gpio_in(mpicdev, 42), 399193, serial_hds[1], DEVICE_BIG_ENDIAN); } =20 @@ -896,7 +890,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) qdev_init_nofail(dev); s =3D SYS_BUS_DEVICE(dev); for (i =3D 0; i < PCI_NUM_PINS; i++) { - sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]); + sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])= ); } =20 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, @@ -927,7 +921,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) dev =3D qdev_create(NULL, "mpc8xxx_gpio"); s =3D SYS_BUS_DEVICE(dev); qdev_init_nofail(dev); - sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IR= Q)); memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, sysbus_mmio_get_region(s, 0)); =20 @@ -947,7 +941,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) =20 for (i =3D 0; i < params->platform_bus_num_irqs; i++) { int irqn =3D params->platform_bus_first_irq + i; - sysbus_connect_irq(s, i, mpic[irqn]); + sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); } =20 memory_region_add_subregion(address_space_mem, --=20 2.11.0