From nobody Wed Feb 11 02:54:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508215470158942.0688513633072; Mon, 16 Oct 2017 21:44:30 -0700 (PDT) Received: from localhost ([::1]:36450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e4Jju-0002FO-Ar for importer@patchew.org; Tue, 17 Oct 2017 00:44:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e4JOe-0008Tz-62 for qemu-devel@nongnu.org; Tue, 17 Oct 2017 00:22:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e4JOb-0007C2-82 for qemu-devel@nongnu.org; Tue, 17 Oct 2017 00:22:28 -0400 Received: from ozlabs.org ([103.22.144.67]:36949) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e4JOa-00078i-RH; Tue, 17 Oct 2017 00:22:25 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3yGMTx5qRvz9t69; Tue, 17 Oct 2017 15:22:11 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1508214133; bh=YJD8DeYGPc94KMbZyKHDZJ64uwwjBbYRMkF9bVv4Nm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FyZuJbOpd8mhRJQJJ9mypw3DXadq5288viaIz+bJ9jViMkWslJcOZdp7pClfdvd+X HFaEd73vzKs+phMYaUe9xMftSaAhSELV29JmlPuQtpaFctP34DgQvvIZkEuNy/KT10 5SdE6j03XgFL4RSwQz2iZhCtSNWO9aom9UgIPybg= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 17 Oct 2017 15:21:48 +1100 Message-Id: <20171017042152.29443-31-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171017042152.29443-1-david@gibson.dropbear.id.au> References: <20171017042152.29443-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 30/34] ppc: pnv: drop PnvChipClass::cpu_model field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: agraf@suse.de, ehabkost@redhat.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, imammedo@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: David Gibson --- hw/ppc/pnv.c | 25 +++++++++++++------------ hw/ppc/pnv_core.c | 5 ----- include/hw/ppc/pnv.h | 1 - include/hw/ppc/pnv_core.h | 1 - 4 files changed, 13 insertions(+), 19 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1e78b685a3..80c7f62bbc 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -55,6 +55,16 @@ #define KERNEL_LOAD_ADDR 0x20000000 #define INITRD_LOAD_ADDR 0x40000000 =20 +static const char *pnv_chip_core_typename(const PnvChip *o) +{ + const char *chip_type =3D object_class_get_name(object_get_class(OBJEC= T(o))); + int len =3D strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); + char *s =3D g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type= ); + const char *core_type =3D object_class_get_name(object_class_by_name(s= )); + g_free(s); + return core_type; +} + /* * On Power Systems E880 (POWER8), the max cpus (threads) should be : * 4 * 4 sockets * 12 cores * 8 threads =3D 1536 @@ -269,8 +279,7 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) =20 static void powernv_populate_chip(PnvChip *chip, void *fdt) { - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i; =20 @@ -300,7 +309,6 @@ static void powernv_populate_chip(PnvChip *chip, void *= fdt) powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } - g_free(typename); } =20 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -712,7 +720,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8e_v2.1"; k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; @@ -734,7 +741,6 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8_v2.0"; k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -756,7 +762,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8nvl_v1.0"; k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -778,7 +783,6 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power9_v2.0"; k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask =3D POWER9_CORE_MASK; @@ -853,7 +857,7 @@ static void pnv_chip_init(Object *obj) static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i, j; char *name; @@ -878,8 +882,6 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error *= *errp) memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); } } - - g_free(typename); } =20 static void pnv_chip_realize(DeviceState *dev, Error **errp) @@ -887,7 +889,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) PnvChip *chip =3D PNV_CHIP(dev); Error *error =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i, core_hwid; =20 @@ -946,7 +948,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) &PNV_CORE(pnv_core)->xscom_regs); i++; } - g_free(typename); =20 /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 350394fdb5..82ff440b33 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -246,9 +246,4 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE("power9_v2.0"), }; =20 -char *pnv_core_typename(const char *model) -{ - return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model); -} - DEFINE_TYPES(pnv_core_infos) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f1bfa6c499..59524cd42b 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -69,7 +69,6 @@ typedef struct PnvChipClass { SysBusDeviceClass parent_class; =20 /*< public >*/ - const char *cpu_model; PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index a336a1f18a..e337af7a3a 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -46,6 +46,5 @@ typedef struct PnvCoreClass { =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX -extern char *pnv_core_typename(const char *model); =20 #endif /* _PPC_PNV_CORE_H */ --=20 2.13.6